Chia-Shiung Tsai

A leading-edge 0.9µm pixel CMOS image sensor technology with backside illumination: Future challenges for pixel scaling

This paper presents process breakthroughs that enable a BSI 0.9µm pixel formation and its performance. The technology was developed using 300mm bulk silicon starting wafers with the state-of-the-art tool set for BSI sensor processing. This is the first demonstration of 0.9µm BSI pixel with acceptable optical performance. Further improvements are in the area of crosstalk suppression and color performance enhancement for continuous pixel scaling from 0.9µm.

Air-gap guard ring for pixel sensitivity and crosstalk improvement in deep sub-micron CMOS image sensor

An air-gap guard ring around the pixel sensor, to improve pixel sensitivity and crosstalk, in 0.18 /spl mu/m CMOS image sensor technology has been successfully developed. By using the RI (refractive index) difference between the air gap (RI/spl sim/1) and dielectric films (RI=1.4/spl sim/1.6), the major incident light is collected in the targeted pixel due to the total internal reflection occurred in the air-gap/dielectric-film interface. The small pixel pitch of 2.8 /spl mu/m/spl sim/4.0 /spl mu/m has been characterized and demonstrates excellent optical performance. For a 3.0 /spl mu/m pixel, the pixel sensitivity shows 45% enhancement and optical spatial crosstalk achieves 90% reduction at 20/spl deg/ incident angle.

High performance 300mm backside illumination technology for continuous pixel shrinkage

Backside Illumination (BSI) sensor with excellent optical performance has become the main-stream CMOS image sensor process. This work addressed the key factors and issues for 300mm BSI technology, including wafer distortion, silicon thickness variation, backside junction formation and dielectric film structure, thermal annealing and so on. It is demonstrated that with the optimized key process, a high performance 0.9um BSI pixel with low noise can be fabricated.

A high-performance, high-density 28nm eDRAM technology with high-K/metal-gate

This paper presents industrys smallest 0.035um2 high performance embedded DRAM cell with cylinder-type Metal-Insulator-Metal (MIM) capacitor and integrated into 28nm High-K Metal Gate (HKMG) logic technology. This eDRAM memory features an HKMG CMOS compatible (low-thermal low-charging process) high-K MIM capacitor with extreme low leakage (<0.1fA/cell). Access transistor with HKMG shows excellent driving capability (>50uA/cell) with <1fA/cell leakage in 28nm cell and <3fA/cell in 20nm cell (0.021um2). We demonstrate first functional silicon success of 28nm eDRAM macro. 600/550 MHz operating frequency is achieved at typical/worse cases.

A manufacturable interposer MIM decoupling capacitor with robust thin high-K dielectric for heterogeneous 3D IC CoWoS wafer level system integration

A reliability proven high-K (HK) metal-insulator-metal (MiM) structure has been verified within the silicon interposer in a chip-on-wafer-on-substrate (CoWoS) packaging for heterogeneous system-level decoupling application. The HK dielectric has an equivalent oxide thickness (EOT) of 20Å, intrinsic TDDB lifetime of 322 years at an operation voltage (V_cc) of 1.8V, and a leakage current (I_LK) below 1 fA/μm² under +/-2V bias at 125°C. The measured unit area capacitance density for the single, 2- and 3-in-series Si-interposer HK-MiM combination is 17.2, 4.3 and 1.9 fF/μm², respectively, with their corresponding I_LK below 0.48, 0.19 and 0.09 fAmp/μm². Process reliability related defect density (D₀) of the interposer HK-MiM is as low as 0.095% cm^-2 as judged by a 10 years lifetime breakdown voltage (V_bd) criterion at V_cc=3.2V. This low D₀ ensures the Si-interposer HK-MiM to be used in a large area over 1056 cm² within the Si interposer. Moreover, the V_bd tolerance of the HK-MiM can be drastically enhanced to be 9.75 and 14.25V, respectively, by 2- and 3-in-series HK-MiM configuration connection. At the package level during all steps of CoWoS processing, no distinguishable process induced damage (PID) and performance degradation (Cap., I_LK & V_bd tailing) were detected. Therefore, this high capacitance, low leakage, large area and reliability-proven Si-interposer decoupling capacitor (DeCAP) within CoWoS greatly enhances the merit of using Si-interposer HK-MiM capacitors for multi-chip system-level integration.

A high density cylinder-type MIM capacitor integrated with advanced 28nm logic High-K/Metal-Gate process for embedded DRAM

A cylinder-type Metal-Insulator-Metal (MIM) capacitor integrated with advanced 28nm logic High-K/Metal-Gate (HKMG) process for embedded DRAM has been developed. The stacked cell capacitor is formed using low temperature high-K dielectrics to achieve sufficient storage capacitance without significantly impacting logic transistors. This paper describes techniques to achieve cylinder-type MIM capacitors capacitance >;10fF/cell and keep the low leakage (<;0.1fA/cell) requirements. The MIM dielectric reliability test passes Time Dependent Dielectric Breakdown (TDDB) lifetime (>;10 years). The test vehicle is composed of 72 macros of 4.5Mb each. We successfully demonstrate fully functional good yield of 28nm eDRAM 324Mb test vehicle with access speed >;330MHz.

Using an ammonia treatment to improve the floating-gate spacing in split-gate flash memory

In the split-gate flash memory process, during poly oxidation, the birds beak encroaches under the SiN film, especially along the poly grain boundary, and that will cause nonuniform floating-gate (FG) spacing, even bridging, which is an obstacle to cell shrinkage. In this paper, we show that employing an ammonia treatment on the poly can nitridize the poly surface, thereby avoiding birds beak bridging. After the ammonia treatment, FG spacing is quite uniform and can be improved from 0.09 to 0.03 /spl mu/m. The XPS analysis on the ammonia treated poly shows the oxynitride thickness is less than 5 nm.

Plasma charging defect characterization, inspection, and monitors in poly-buffered STI

In this paper, the mechanism, inspection, and inline monitor of plasma charging defects found in an active area (AA) corner and edge using a poly-buffer (PB) STI process is reported. These defects are formed by the arcing (or discharging) through weak spots of pad-oxide between the poly-buffer layer and substrate as resulting from the charging of poly buffer layer during reverse-AA oxide etching. Such defect formation is found to be strongly enhanced by the magnetic field used in oxide etchers but not related to etch rate and plasma density. The defect inspection on patterned wafers is found to be strongly correlated to the flat-band voltage (V/sub fb/) and to a lesser extent to oxide charge (Q/sub tot/) degradation on in-line unpatterned oxide wafers. Therefore, the shift of V/sub tb/ and Q/sub tot/ on unpatterned wafers can be effective inline monitors for plasma charging damage during reverse-AA etching in PB-STI process.