Yevgeny Perelman

An Integrated System for Multichannel Neuronal Recording With Spike/LFP Separation, Integrated A/D Conversion and Threshold Detection

A mixed-signal front-end processor for multichannel neuronal recording is described. It receives 12 differential-input channels of implanted recording electrodes. A programmable cutoff High Pass Filter (HPF) blocks dc and low-frequency input drift at about 1 Hz. The signals are band-split at about 200 Hz to low-frequency Local Field Potential (LFP) and high-frequency spike data (SPK), which is band limited by a programmable-cutoff LPF, in a range of 8-13 kHz. Amplifier offsets are compensated by 5-bit calibration digital-to-analog converters (DACs). The SPK and LFP channels provide variable amplification rates of up to 5000 and 500, respectively. The analog signals are converted into 10-bit digital form, and streamed out over a serial digital bus at up to 8 Mbps. A threshold filter suppresses inactive portions of the signal and emits only spike segments of programmable length. A prototype has been fabricated on a 0.35-mum CMOS process and tested successfully, demonstrating a 3-muV noise level. Special interface system incorporating an embedded CPU core in a programmable logic device accompanied by real-time software has been developed to allow connectivity to a computer host

Low-Power Architectures for Spike Sorting

Front-end integrated circuits for spike sorting will be useful in neuronal recording systems that engage a large number of electrodes. Detecting, sorting and encoding spike data at the front-end will reduce the data bandwidth and enable wireless communication. Without such data reduction, large data volumes need to be transferred to a host computer and typically heavy cables are required which constrain the patient or test animal. Front-end processing circuits must dissipate only a limited amount of power, due to supply constraints and heat restrictions. Two reduced complexity spike sorting algorithms are introduced, one based on integral transform and another on segmented PCA. The former achieves 98% of the precision of a PCA sorter, while requiring only 2.5% of the computational complexity. The latter algorithm is somewhat more accurate but incurs a higher complexity

High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link

A high data rate asynchronous bit-serial link for long-range on-chip communication is presented. The data bit cycle time is equal to a single gate delay, enabling 67 Gbps throughput in 65 nm technology. The serial link incurs lower power and area costs relative to bit-parallel communications, and enables higher tolerance to PVT variations relative to synchronous links. The link uses differential dual-rail level encoding (LEDR) and current mode signaling over a low-crosstalk interconnect layout. Novel circuits used in the link are described, including a novel splitter shift register, a fast LEDR encoder, a high-speed toggle element, a channel driver with adaptive control and a differential channel receiver.

A low-light-level sensor for medical diagnostic applications

A low-level light sensor and preprocessor for a disposable medical probe is described. A 10-Hz 4-/spl mu/A/cm/sup 2/ input optical signal in the visible spectrum is assumed in chemoluminant diagnostic applications. A single-bit first-order sigma-delta modulator has been employed for analog-to-digital conversion, thanks to its robustness, simplicity, inherent linearity, and high signal-to-noise ratio. A current buffer has been used to replicate the weak signal with sufficient bandwidth. Tests have shown the feasibility of this approach, and have also enabled improvements of the design.

Algorithms and architectures for low power spike detection and alignment

We introduce algorithms and architectures for automatic spike detection and alignment that are designed for low power. Some of the algorithms are based on principal component analysis (PCA). Others employ a novel integral transform analysis and achieve 99% of the precision of a PCA detector, while requiring only 0.05% of the computational complexity. The algorithms execute autonomously, but require off-line training and setting of computational parameters. We employ pre-recorded neuronal signals to evaluate the accuracy of the proposed algorithms and architectures: the recorded data are processed by a standard PCA spike detection and alignment software algorithm, as well as by the several hardware algorithms, and the outcomes are compared.

Analog Frontend for Multichannel Neuronal Recording System with Spike and LFP Separation

A 0.35microm CMOS integrated circuit for multi-channel neuronal recording with twelve true-differential channels, band separation and digital offset calibration is presented. The measured signal is separated into a low-frequency local field potential and high-frequency spike data. Digitally programmable gains of up to 60 and 80 dB for the local field potential and spike bands are provided. DC offsets are compensated on both bands by means of digitally programmable DACs. Spike band is limited by a second order low-pass filter with digitally programmable cutoff frequency. The IC has been fabricated and tested. 3microV input referred noise on the spike data band was measured.

A low-power inverted ladder D/a converter

Interpolating, dual resistor ladder digital-to-analog converters (DACs) typically use the fine, least significant bit (LSB) ladder floating upon the static most significant bit (MSB) ladder. The usage of the LSB ladder incurs a penalty in dynamic performance due to the added output resistance and switch matrix parasitic capacitance. Current biasing of the LSB ladder addresses this issue by employing active circuitry. We propose an inverted ladder DAC, where an MSB ladder slides upon two static LSB ladders. While using no active components this scheme achieves lower output resistance and parasitic capacitance for a given power budget. We present a 0.35-mum, 3.3-V implementation consuming 22-muA current with output resistance of 40 kOmega and effective parasitic capacitance of 650 fF

An Integrated System for Multichannel Neuronal Recording with Spike / LFP Separation and Digital Output

A mixed-signal front-end processor for multichannel neuronal recording is described. It receives twelve differential-input channels of implanted recording electrodes. A programmable cutoff HPF blocks DC and low frequency input drift. The signals are band-split at about 200 Hz to low frequency local field potential (LFP) and high-frequency spike data (SPK), which is band limited by a programmable-cutoff LPF. Amplifier offsets are compensated by calibration DACs. The SPK and LFP channels provide variable amplification rates of up to 5000 and 500, respectively. The analog signals are converted into digital form, and streamed out over a serial digital bus. A threshold filter supresses inactive portions of the signal and emits only spike segments. A prototype has been fabricated on a 0.35/mum CMOS process and tested successfully

A Low-Power Spike Detection and Alignment Algorithm

Front-end integrated circuits for signal processing are useful in neuronal recording systems that engage a large number of electrodes. Detecting, alignment, and sorting the spike data at the front-end reduces the data bandwidth and enables wireless communication. Without such data reduction, large data volumes need to be transferred to a host computer and typically heavy cables are required which constrain the patient or test animal. Front-end processing circuits can dissipate only a limited amount of power, due to supply constraints and heat restrictions. Reduced complexity spike detection and alignment algorithm and architecture, based on integral transform, are introduced. They achieve 99% of the precision of a PCA detector, while requiring only 0.05% of the computational complexity