Yi-Chung Chen

Non-volatile 3D stacking RRAM-based FPGA

We demonstrates a novel Field-Programmable Gate Array (FPGA) structure based on Resistive Random Access Memory (RRAM) system. RRAM is a non-volatile memory device which is compatible to CMOS Back End of Line (BEOL) process with only 4F2 area per cell. We use a 1R system memory for logic element, Look-Up-Table (LUT), with three dimension stacking structure. The proposed 2R memory system is for routing elements, Switch Block (SB) and Connection Block (CB), with Complementary Resistive Switches (CRS) structure. Both three dimension stacking and CRS structure are crossbar-like structure to further improve density of the FPGA. The proposed design is different from modern FPGA with Static Random Access Memory (SRAM) system, RRAM-based FPGA has benefits of non-volatility, smaller area, and flexibility of configuration. A bit-addressable LUT is introduced with function of run-time programming memory cells of LUT, which is also known as Distributed Random Access Memory (D-RAM). Based on our simulation results, 62.7% of area reduction and 34% of delay improvement can be achieved compared to the conventional FPGA.

The 3-D Stacking Bipolar RRAM for High Density

For its simple structure, high density, and good scalability, the resistive random access memory (RRAM) has emerged as one of the promising candidates for large data storage in computing systems. Moreover, building up RRAM in a 3-D stacking structure further boosts its advantage in array density. Conventionally, multiple bipolar RRAM layers are piled up vertically separated with isolation material to prevent signal interference between the adjacent memory layers. The process of the isolation material increases the fabrication cost and brings in the potential reliability issue. To alleviate the situation, we introduce two novel 3-D stacking structures built upon bipolar RRAM crossbars that eliminate the isolation layers. The bigroup operation scheme dedicated for the proposed designs to enable multilayer accesses while avoiding the overwriting induced by the cross-layer disturbance is also presented. Our simulation results show that the proposed designs can increase the capacity of a memory island to 8K-bits (i.e., eight layers of 32 × 32 crossbar arrays) while maintaining the sense margin in the worst case configuration greater than 20% of the maximal sensing voltage.

A novel peripheral circuit for RRAM-based LUT

Resistive random access memory (RRAM) is a promising candidate to substitute static random access memory (SRAM) in lookup table (LUT) design for its high density and non-volatility. RRAM cells are fabricated at backend CMOS process and have negligible area cost. However, the complex peripheral circuit design to satisfy performance and accuracy requirements becomes a major issue. In this work, we propose a novel peripheral circuit for RRAM-based LUT. A new decoding scheme that supports dynamic programming is introduced. Furthermore, the expanded RRAM crossbar array together with the latch comparator based sense amplifier can dramatically reduce design complexity, decrease area cost, and improve tolerance on process variations. Compared to a 6-input SRAM-based LUT, the proposed RRAM-based one cuts off 60.4% of layout area. The maximal operating frequency reaches 1GHz at 10mV input difference. Simulations also show that the proposed LUT functions properly even RRAM resistances deviates 20% from the design value.

A Look Up Table design with 3D bipolar RRAMs

Look Up Table (LUT) is a basic configurable logic element in Field Programmable Gate Arrays (FPGAs). In a commercial product, Static Random Access Memory (SRAM) has been widely used in each LUT to store configured logic. Recently, emerging Resistive RAM (RRAM) has attracted a lot of attention for its high density and non-volatility. In this work, we explore a novel LUT design with bipolar RRAM deviLUT design with bipolar RRAM devices. To obtain design efficiency, a 3D high-density interleaved memory structure is introduced in the proposed LUT. The corresponding peripheralces. To obtain design efficiency, a 3D high-density interleaved memory structure is introduced in the proposed LUT. The corresponding peripheral circuits were developed with TSMC 0.18μm technology node. Compared to the traditional SRAM-based FPGA, the RRAM-based LUT demonstrates advantages such as a eliminating initialization stage, a much higher density with 56% area reduction, a bit-addressable write scheme, dynamic reconfiguration, and better flexibility in supporting various configurations.

3D-HIM: A 3D High-density Interleaved Memory for bipolar RRAM design

Because of its simple structure, high density and good scalability, resistive random access memory (RRAM) is expected to be a promising candidate to substitute traditional data storage devices, e.g., hard-disk drive (HDD). In a conventional three-dimensional (3D) bipolar RRAM design, an isolation layer is inserted between two adjacent memory layers. The fabrication of the isolation layer introduces the extra process complexity, increases fabrication cost, and causes some potential reliability issues. In this paper, we propose a 3D High-density Interleaved Memory (3D-HIM) design for bipolar RRAM, which can eliminate the need for forming isolation layers and further improve the density of the memory island. Meanwhile, we propose a Bi-Group Operation Scheme for 3D-HIM to access multiple cells among multiple layers and to avoid unexpected overwriting. The simulation results show that the proposed design is promising for a 3D stacking RRAM application with acceptable operation margin for a 32 × 32 × 8 array in a memory island. The sensing margin degradation and programming bias confine the size of the array due to sneak path conducting currents. We diminish impact of sneak path conducting current by applying a high Ron RRAM device which can be achieved by a small-scale RRAM device.

uBRAM-based run-time reconfigurable FPGA and corresponding reconfiguration methodology

With rising demands for high-performance computing and design flexibility of post-fabrication system, reconfigurable architecture has been drawing increasing attentions. However, reconfigurability, advantage of current Field-Programmable Gate Array (FPGA), is severely limited by small capacity of on-chip Static Random Access Memory (SRAM) for storing configuration bits. With emerging high-density and high-performance nano memory devices, opportunities are provided to improve the reconfigurability of the current FPGAs design.

3D-ICML: A 3D bipolar ReRAM design with interleaved complementary memory layers

Resistive random access memory (ReRAM) has been demonstrated as a promising non-volatile memory technology with features such as high density, low power, good scalability, easy fabrication and compatibility to the existing CMOS technology. The conventional three-dimensional (3D) bipolar ReRAM design usually stacks up multiple memory layers that are separated by isolation layers, e.g. Spin-on-Glass (SOG). In this paper, we propose a new 3D bipolar ReRAM design with interleaved complimentary memory layers (3D-ICML) which can form a memory island without any isolation. The set of metal wires between two adjacent memory layers in vertical direction can be shared. 3D-ICML design can reduce fabrication complexity and increase memory density. Meanwhile, multiple memory cells interconnected horizontally and vertically can be accessed at the same time, which dramatically increases the memory bandwidth.

A hardware security scheme for RRAM-based FPGA

To enhance the system integrity of FPGA-based embedded systems on hardware design, we propose a hardware security scheme for nonvolatile resistive random access memory (RRAM) based FPGA, in which internal block RAM (BRAMs) are used for configuration and temporary data storage. The proposed scheme loads obfuscated configurations into nonvolatile BRAMs to protect design data from physical attacks and utilizes Chip DNA to enable logic function.

IC thermal analyzer for versatile 3-D structures using multigrid preconditioned krylov methods

Thermal analysis is crucial for determining the propagation of heat and tracking the formation of hot spots in advanced integrated circuit technologies. At the core of the thermal analysis for integrated circuits is the numerical solution of the heat equation. Prior academic thermal analysis tools typically compute temperature by applying finite difference methods on uniform grids with time integration methods having fixed time step size. Additionally, the linear systems arising from the discretized heat equation are solved using direct methods based on matrix factorizations. Direct methods, however, do not scale well as the problem size increases. Moreover, most of the tools support only 2-D or a limited number of 3-D technologies. To address these issues, this paper presents a novel thermal analyzer with the ability to model both 2-D and 3-D circuit technologies. The analyzer solves the heat equation using the finite element method for the spatial discretization coupled with implicit time integration methods for advancing the solution in time. It also offers fully adaptive spatio-temporal refinement features for improved accuracy and computational efficiency. The resulting linear systems are solved by a multigrid preconditioned Krylov subspace iterative method, which gives superior performance for 3-D transient analyses. The analyzer is shown to accurately capture the propagation of heat in both the horizontal and vertical directions of integrated systems.

Computationally efficient standard-cell FEM-based thermal analysis

Thermal analysis of integrated circuits (IC) is a high performance computing problem because the nanoscale spatiotemporal features of the problem result in a large discrete problem. In previous works, compact models of ICs were introduced to speed up the modeling process. However, such methods have limited accuracy as they approximate the underlying physics. They are also ill-suited to simulate the thermal characteristics of an IC at the cell-level. The finite element method (FEM) is an appropriate computational technique for providing both fast and accurate thermal analyses. Considering that the number of cells in modern ICs is on the order of millions, thermal analysis at this abstraction level is a formidable task. Consequently, handling the computational meshes and computing thermal profiles of an IC at the cell-level requires substantial computing power. In order to provide accurate cell-level thermal simulations at a lower computational cost, this work introduces advanced techniques that judiciously trade off mesh granularity with simulation accuracy which allows fast analysis of cell-level floorplans. The proposed cell-homogenization techniques start with a flat cell-level floorplan and a related power trace and produce reduced order meshes that accelerate thermal simulations with a negligible loss in accuracy. Results show that the proposed techniques achieve up to a 90% reduction in the number of nodes in the mesh with less than 5% error in the temperature compared to the full scale mesh. The simulation time is also reduced by an order of magnitude.