Robinson E. Pino

A Memristor Device Model

This letter proposes a new mathematical model for memristor devices. It builds on existing models and is correlated against several published device characterizations. This letter identifies significant discrepancies between the existing models and published device characterization data. The proposed model addresses these discrepancies. In particular, it allows modeling of memristor-based neuromorphic systems.

Leveraging Memristive Systems in the Construction of Digital Logic Circuits

The recent emergence of the memristor has led to a great deal of research into the potential uses of the devices. Specifically, the innate reconfigurability of memristors can be exploited for applications ranging from multilevel memory, programmable logic, and neuromorphic computing, to name a few. In this work, memristors are explored for their potential use in dense programmable logic circuits. While much of the work is focused on Boolean logic, nontraditional styles including threshold logic and neuromorhpic computing are also considered. In addition to an analysis of the circuits themselves, computer-aided design (CAD) flows are presented which have been used to map digital logic functionality to dense complementary metal-oxide-semiconductor (CMOS)-memristive logic arrays. As exemplified through the circuits described here memristor-based digital logic holds great potential for high-density and energy-efficient computing.

Geometry variations analysis of TiO 2 thin-film and spintronic memristors

The fourth passive circuit element, memristor, has attracted increased attentions since the first real device was discovered by HP Lab in 2008. Its distinctive characteristic to record the historic profile of the voltage/current through itself creates great potentials in future system design. However, as a nano-scale device, memristor is facing great challenge on process variation control in the manufacturing. In this work, we analyze the impact of the geometry variations on the electrical properties of both TiO2 thin-film and spintronic memristors, including line edge roughness and thickness fluctuation. A simple algorithm was proposed to generate a large volume of geometry variation-aware three-dimensional device structures for Monte-Carlo simulations. Our simulation results show that due to the different physical mechanisms, TiO2 thin-film memristor and spintronic memristor demonstrate very different electrical characteristics even when exposing them to the same excitations and under the same process variation conditions.

Advances in Neuromorphic Memristor Science and Applications

Physical implementation of the memristor at industrial scale sparked the interest from various disciplines, ranging from physics, nanotechnology, electrical engineering, neuroscience, to intelligent robotics. As any promising new technology, it has raised hopes and questions; it is an extremely challenging task to live up to the high expectations and to devise revolutionary and feasible future applications for memristive devices. The possibility of gathering prominent scientists in the heart of the Silicon Valley given by the 2011 International Joint Conference on Neural Networks held in San Jose, CA, has offered us the unique opportunity of organizing a series of special events on the present status and future perspectives in neuromorphic memristor science. This book presents a selection of the remarkable contributions given by the leaders of the field and it may serve as inspiration and future reference to all researchers that want to explore the extraordinary possibilities given by this revolutionary concept.

Compact method for modeling and simulation of memristor devices: ion conductor chalcogenide-based memristor devices

A compact model and simulation methodology for chalcogenide based memristor devices is proposed. From a microprocessor design view point, it is important to be able to simulate large numbers of devices within the integrated circuit architecture in order to speed up reliably the development process. Ideally, device models would accurately describe the characteristic device behavior and would be represented by single-valued equations without requiring the need for recursive or numerically intensive solutions. With this in mind, we have developed an empirical chalcogenide compact memristor model that accurately describes all regions of operations of memristor devices employing single-valued equations.

Memristor SPICE model and crossbar simulation based on devices with nanosecond switching time

This paper presents a memristor SPICE model that is able to reproduce current-voltage relationships of previously published memristor devices. This SPICE model shows a stronger correlation to various published device data when compared to existing SPICE models. Furthermore, switching characteristics of published memristor devices with switching times in the nanosecond scale were modeled. Therefore, this model can be used to accurately simulate neural systems based on these high-speed memristors. This paper also demonstrates how this model can be used to accurately calculate switching energy of these high-speed devices, leading to more accurate power calculations in memristor based neural systems. Memristor crossbar circuits provide a potential method for developing very high density neural classifiers. This model was able to simulate crossbar circuits containing up to 256 memristors. It is significantly less likely to cause convergence errors when operating in the nanosecond switching regime with a large number of devices when compared with existing SPICE models.

Memristor-Based Neural Logic Blocks for Nonlinearly Separable Functions

Neural logic blocks (NLBs) enable the realization of biologically inspired reconfigurable hardware. Networks of NLBs can be trained to perform complex computations such as multilevel Boolean logic and optical character recognition (OCR) in an area- and energy-efficient manner. Recently, several groups have proposed perceptron-based NLB designs with thin-film memristor synapses. These designs are implemented using a static threshold activation function, limiting the set of learnable functions to be linearly separable. In this work, we propose two NLB designs-robust adaptive NLB (RANLB) and multithreshold NLB (MTNLB)-which overcome this limitation by allowing the effective activation function to be adapted during the training process. Consequently, both designs enable any logic function to be implemented in a single-layer NLB network. The proposed NLBs are designed, simulated, and trained to implement ISCAS-85 benchmark circuits, as well as OCR. The MTNLB achieves 90 percent improvement in the energy delay product (EDP) over lookup table (LUT)-based implementations of the ISCAS-85 benchmarks and up to a 99 percent improvement over a previous NLB implementation. As a compromise, the RANLB provides a smaller EDP improvement, but has an average training time of only ≈ 4 cycles for 4-input logic functions, compared to the MTNLBs ≈ 8-cycle average training time.

A Parallel Neuromorphic Text Recognition System and Its Implementation on a Heterogeneous High-Performance Computing Cluster

Given the recent progress in the evolution of high-performance computing (HPC) technologies, the research in computational intelligence has entered a new era. In this paper, we present an HPC-based context-aware intelligent text recognition system (ITRS) that serves as the physical layer of machine reading. A parallel computing architecture is adopted that incorporates the HPC technologies with advances in neuromorphic computing models. The algorithm learns from what has been read and, based on the obtained knowledge, it forms anticipations of the word and sentence level context. The information processing flow of the ITRS imitates the function of the neocortex system. It incorporates large number of simple pattern detection modules with advanced information association layer to achieve perception and recognition. Such architecture provides robust performance to images with large noise. The implemented ITRS software is able to process about 16 to 20 scanned pages per second on the 500 trillion floating point operations per second (TFLOPS) Air Force Research Laboratory (AFRL)/Information Directorate (RI) Condor HPC after performance optimization.

Memristor-based synapse design and training scheme for neuromorphic computing architecture

Memristors have been rediscovered recently and then gained increasing attentions. Their unique properties, such as high density, nonvolatility, and recording historic behavior of current (or voltage) profile, have inspired the creation of memristor-based neuromorphic computing architecture. Rather than the existing crossbar-based neuron network designs, we focus on memristor-based synapse and the corresponding training circuit to mimic the real biological system. In this paper, first, the basic synapse design is presented. On top of it, we will discuss the training sharing scheme and explore design implication on multi-synapse neuron system. Energy saving method such as self-training is also investigated.

Statistical memristor modeling and case study in neuromorphic computing

Memristor, the fourth passive circuit element, has attracted increased attention since it was rediscovered by HP Lab in 2008. Its distinctive characteristic to record the historic profile of the voltage/current creates a great potential for future neuromorphic computing system design. However, at the nano-scale, process variation control in the manufacturing of memristor devices is very difficult. The impact of process variations on a memristive system that relies on the continuous (analog) states of the memristors could be significant. We use TiO2-based memristor as an example to analyze the impact of geometry variations on the electrical properties. A simple algorithm was proposed to generate a large volume of geometry variation-aware three-dimensional device structures for Monte-Carlo simulations. A neuromorphic computing system based on memristor-based bidirectional synapse design is proposed as case study. We analyze and evaluate the robustness of the proposed system in pattern recognition based on massive Monte-Carlo simulations, after considering input defects and process variations.