Yi-Hsien Chang
TSMC
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Publication
Featured researches published by Yi-Hsien Chang.
international electron devices meeting | 2015
K.-Y. Roy Wong; Man-Ho Kwan; Fu-Wei Yao; M.W. Tsai; Yen-Chun Lin; Yi-Hsien Chang; Po-Chih Chen; R.-Y. Su; J. L. Yu; Fu-Chih Yang; G. P. Lansbergen; Chih-Wen Hsiung; Y.-A. Lai; K.-L. Chiu; Chang‐Nan Chen; M.-C. Lin; H.-Y. Wu; C.-H. Chiang; Sheng-Da Liu; Han-Chin Chiu; P.-C. Liu; Claire Chen; Chung-Yi Yu; Chia-Shiung Tsai; C.-B. Wu; B. Lin; M.-H. Chang; Jan-Wen You; S.-P. Wang; L.-C. Chen
CMOS-compatible 100 V / 650 V enhancement-mode high electron mobility transistors (E-HEMTs) and 650 V depletion-mode MISFET (D-MISFET) are fabricated on 6-inch GaN-on-Si wafers. These devices show excellent power converter switching performances. Both 100 V and 650 V E-HEMTs had passed industrial reliability qualifications. The importance of bulk leakage, interface quality and gate trapping in dynamic on-resistance is figured out. The device with optimized processes shows a significant reduction of the dynamic on-resistance degradation.
international electron devices meeting | 2014
Man Ho Kwan; King-Yuen Wong; Y. S. Lin; Fu-Wei Yao; M.W. Tsai; Yi-Hsien Chang; P. C. Chen; Ru-Yi Su; Cheng-Hsien Wu; J. L. Yu; F. J. Yang; G. P. Lansbergen; H.-Y. Wu; M.-C. Lin; C.-B. Wu; Y.-A. Lai; Chih-Wen Hsiung; P.-C. Liu; H.-C. Chiu; Ching-Ray Chen; Chung-Yi Yu; Hong-Nien Lin; M.-H. Chang; S.-P. Wang; L.-C. Chen; J. L. Tsai; H. C. Tuan; Alex Kalnitsky
CMOS-compatible 100/650 V enhancement-mode FETs and 650 V depletion-mode MISFETs are fabricated on 6-inch AlGaN/GaN-on-Si wafers. They show high breakdown voltage and low specific on-resistance with good wafer uniformity. The importance of epitaxial quality is figured out in a key industrial item: high-temperature-reverse-bias-stress-induced on-state drain curent degradation. Optimization of epitaxial layers shows significant improvement of device reliability.
international symposium on power semiconductor devices and ic s | 2016
H.-Y. Wu; M.-C. Lin; Nan-Ying Yang; C.T. Tsai; C.-B. Wu; Yen-Chun Lin; Yi-Hsien Chang; Po-Chih Chen; King-Yuen Wong; Man-Ho Kwan; C.Y. Chan; Fu-Wei Yao; M.W. Tsai; C.L. Yeh; R.-Y. Su; J. L. Yu; Fu-Chih Yang; J. L. Tsai; H. C. Tuan; Alex Kalnitsky
GaN Cascode performance optimization for high efficient power applications is presented in this paper. Analytical equations of Cascode capacitance network (Ciss, Coss, Cgd) is demonstrated and the equations accuracy is verified through experimental measurement. Analysis shows that Cascode Cgd is determined by HV D-MISFETs Cds, LV Si FETs Cgd/Coss ratio, and extra zener diode capacitance. With low intrinsic capacitance HV D-MISFETs [1-2], proper LV Si FETs selection, and extra zener diode protection, optimization for Cascode switching figure-of-merit (FOM, Ron x Qgd) is well demonstrated. 8.8X lower switching figure-of-merit than commercial best-in-class Si SJ FETs [3] is achieved, double pulse test (DPT) and hard switching PFC system verification result all indicate that GaN Cascode is the promising solution and ready for next generation energy systems.
Archive | 2014
Yi-Shao Liu; Chun-Ren Cheng; Ching-Ray Chen; Yi-Hsien Chang; Fei-Lung Lai; Chun-Wen Cheng
Archive | 2015
Wei-Cheng Shen; Yi-Hsien Chang; Shih-wei Lin; Chun-Ren Cheng
Archive | 2013
Chia-Hua Chu; Allen Timothy Chang; Ching-Ray Chen; Yi-Hsien Chang; Yi-Shao Liu; Chun-Ren Cheng; Chun-Wen Cheng
Archive | 2013
Wei-Cheng Shen; Yi-Shao Liu; Yi-Hsien Chang; Chun-Ren Cheng
Archive | 2012
Yi-Hsien Chang; Chun-Ren Cheng; Yi-Shao Liu; Allen Timothy Chang; Ching-Ray Chen; Yeh-Tseng Li; Wen-Hsiang Lin
Archive | 2016
Yi-heng Tsai; Yi-Hsien Chang; Chun-Ren Cheng; Chun-Wen Cheng; Tzu-Heng Wu; Wei-Cheng Shen
Archive | 2010
Chun-Ren Cheng; Yi-Hsien Chang; Allen Timothy Chang; Ching-Ray Chen; Li-Cheng Chu; Hung-Hua Lin; Yuan-Chih Hsieh; Lan-Lin Chao