Yi-Ming Sheu

A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics

This paper demonstrates a new compact and scaleable model of mechanical stress effects on MOS electrical performance, induced by shallow trench isolation (STI). This model has included the influence of STI stress not only on the mobility and saturation velocity, but also on the threshold voltage and other important second-order effects. Thus it could simulate the layout dependence of MOS performance with good accuracy and efficiency. We have verified this model with various device dimensions and layout styles of our advanced MOS technologies. And it shows the importance of this new model for circuit design in advanced CMOS generations.

Modeling mechanical stress effect on dopant diffusion in scaled MOSFETs

The effect of shallow trench isolation mechanical stress on MOSFET dopant diffusion has become significant, and affects device behavior for sub-100-nm technologies. This paper presents a stress-dependent dopant diffusion model and demonstrates its capability to reflect experimental results for a state-of-the-art logic CMOS technology. The proposed stress-dependent dopant diffusion model is shown to successfully reproduce device characteristics covering a wide range of active area sizes, gate lengths, and device operating conditions.

Effects of germanium and carbon coimplants on phosphorus diffusion in silicon

The authors have studied the interactions between implant defects and phosphorus diffusion in crystalline silicon. Defect engineering enables ultrashallow n+∕p junction formation using phosphorus, carbon, and germanium coimplants, and spike anneal. Their experimental data suggest that the positioning of a preamorphized layer using germanium implants plays an important role in phosphorus diffusion. They find that extending the overlap of germanium preamorphization and carbon profiles results in greater reduction of phosphorus transient-enhanced diffusion by trapping more excess interstitials. This conclusion is consistent with the end-of-range defects calculated by Monte Carlo simulation and annealed carbon profiles.

A 65nm node strained SOI technology with slim spacer

A 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 /spl mu/A//spl mu/m for N-FET and P-FET, respectively, at an off-state leakage of 40 nA//spl mu/m using 1 V operation. The technology employs an aggressively scaled slim spacer of 30 nm width to amplify stress benefits for performance improvement, and to reduce by 10-20 % the layout area for SRAM-cell-like circuits, while maintaining excellent hot carrier immunity and well-controlled short-channel effects. For the first time, we demonstrate that FinFET devices, implicitly implemented in this technology, offer a 8-15 % higher inverter speed compared to planar SOI devices at the same drive current.

Modeling well edge proximity effect on highly-scaled MOSFETs

Well edge proximity effect caused by ion scattering during implantation in highly-scaled CMOS technology was explored from a process and physics point of view. TCAD simulation was employed to visualize the internal change of the MOSFETs. A new compact model for SPICE was proposed using physics-based understanding and was calibrated with experimental silicon test sets. Circuit simulation using the proposed model was conducted to evaluate the improvement in accuracy

Molecular Dynamic simulation study of stress memorization in Si dislocations

Stress-Memorization-Technique by Si dislocations is effective in enhancing NFET device performance [1,2]. For the first time, MD (Molecular Dynamic) simulations are applied to explain the formation mechanism of dislocations during the Solid-Phase-Epitaxy-Regrowth (SPER) process. A semi- empirical TCAD method based on lattice-KMC (L-KMC) is then developed to predict dislocation formation. The simulated dislocation positions agree well with silicon experiments characterized by TEM. TCAD simulations show that the resulting dislocations are along the [111] direction and provide ~650MPa average longitudinal stress in channel regions, consistent with Nano-Beam-Diffraction (NBD) strain measurement. The channel stress is predicted by simulation to further increase by 1.5X after the poly-silicon gate removal step in a replacement-gate process. The dislocation SMT enhances NFET electron mobility by 25% and Ion-Ioff performance by 15%.

Impact of STI mechanical stress in highly scaled MOSFETs

Intensive experiment on highly scaled MOSFETs with mask gate lengths down to 90 nm shows significant sensitivities (up to 10 %) of drive current per unit width to the shrinking of active area size down to 0.6 /spl mu/m as well as to the gate placement distance from STI (shallow trench isolation) edge. This suggests the impact of STI induced mechanical stress along the direction of the channel current flow. Even n-and p-channel FETs are observed to behave in opposite trends with respect to the lateral active area size. Mechanical stress simulation of underlying entire front-end process line is conducted also intensively. Systematic analysis turns out strikingly that the experimental drive current sensitivity tracks well the compressive-type strain along the channel, leading to a correlation established between the two. This work promises exploration of mechanical stress issues in future nanoscale devices and circuits.

New Observations in LOD Effect of 45-nm P-MOSFETs With Strained SiGe Source/Drain and Dummy Gate

Length of thin oxide definition area (LOD) effects and the incorporation of the dummy poly gates on the performance of 45-nm P-MOSFETs with and without strained SiGe source/drain (S/D) are systematically investigated. In the non-SiGe devices, the LOD effect is dominated by the STI stress and shows a little dependence of dummy poly gates. However, in the SiGe device, the LOD effect is strongly dependent on the location of the dummy poly gate. For dummy poly gate located outside the active area, the compressive stress from the SiGe S/D dominates the LOD effect, but for dummy poly gate located within the active area, the LOD effect is controlled by both the SiGe S/D stress within the dummy gate and the STI stress. The mechanisms of our new observations are analyzed with TCAD simulations.

Millisecond Anneal and Short-Channel Effect Control in Si CMOS Transistor Performance

In this letter, the effects of the millisecond anneal in conjunction with conventional spike anneal on the p-n junction formation in CMOS devices are studied. The results reveal that the millisecond and spike annealing sequence plays an important role in the implanted boron p+/n junction formation. On blanket Si wafers, the millisecond anneal followed by the spike anneal increases implanted boron solid solubility in crystalline silicon by ~18% compared to that obtained using reversed annealing sequence under the same annealing conditions. This result substantially alters the short-channel effect behaviors in the fabricated CMOS devices, resulting in opposite threshold-voltage behaviors in PMOS and NMOS devices when using boron as NMOS halo implant. The results also provide useful insights into ultrashallow-junction formation and short-channel effect control when scaling CMOS technology

A Novel Approach to Link Process Parameters to BSIM Model Parameters

In this paper, we demonstrate a methodology to link process parameters to BSIM model parameters. Here, we have combined well-known statistical methods like principal component analysis (PCA), design of experiments (DOE), and response surface methodology (RSM) to bridge the missing link between process parameters and model parameters. The proposed methodology uses the concept of a correlation matrix, which transforms the process level information to the device and circuit level information through the BSIM model parameters. The proposed methodology has been successfully implemented on an advanced CMOS process. Our results show a strong linear correlation for the data obtained from two techniques namely TCAD technique and the standard HSPICE simulation technique. In both cases the process conditions were kept identical for comparison.