Stephen H. Tang

Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging

Temperature, voltage, and current sensors monitor the operation of a TCP/IP offload accelerator engine fabricated in 90nm CMOS, and a control unit dynamically changes frequency, voltage, and body bias for optimum performance and energy efficiency. Fast response to droops and temperature changes is enabled by a multi-PLL clocking unit and on-chip body bias. Adaptive techniques are also used to compensate performance degradation due to device aging, reducing the aging guardband.

Ultra-low voltage circuits and processor in 180nm to 90nm technologies with a swapped-body biasing technique

A low-voltage swapped-body biasing technique where PMOS bodies are connected to ground and NMOS bodies to Vcc is evaluated. Available measurements show more than 2.6x frequency improvement at 0.5V Vcc and the ability to reduce Vcc by 0.2V for the same frequency compared to no body bias in 180 to 90nm CMOS technologies.

Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage

Fluctuations in intrinsic linear V/sub T/, free of impact of parasitics, are measured for large arrays of NMOS and PMOS devices on a testchip in a 150nm logic technology. Local intrinsic /spl rho/V/sub T/, free of extrinsic process, length and width variations, is random, and worsens with reverse body bias. Although the traditional area-dependent component is dominant, a significant component of the fluctuations in small devices depends only on device width or length.

Temperature and process invariant MOS-based reference current generation circuits for sub-1V operation

Measurements on a prototype chip, implemented in a 150nm logic process technology, validate the theories for two sub-1V MOS reference current generator circuits and show that 2X reduction in current variation is achievable across extremes of both process and temperature.