Chi-Chun Huang

All-MOS ASK Demodulator for Low-Frequency Applications

A miniature amplitude-shift-keying (ASK) demodulator without any passive elements, i.e., R or C, for low-frequency applications is presented in the paper. The noise margin of the envelope detector in the proposed ASK demodulator is enlarged such that any Schmitt trigger or current limiting resistor is no longer needed. It results in the number of transistors required for the ASK demodulator circuit is reduced to 12, while the area is merely 0.003025 mm2 using 0.35-mum 2P4M CMOS process. The power consumption is found to be 1.01 mW by physical measurement on silicon. The data rate is measured to be 250 kbps for 2-MHz carrier frequency and 27% modulation index.

A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic

A high speed and low power 8-bit carry-lookahead adder using two-phase modified dual-threshold voltage (dual-Vt) domino logic blocks which are arranged in a programmable logical array-like design style with pipelining is presented. The modified domino logic circuits employ dual-transistors and reversed bulk-source biases for reducing subthreshold leakage current when advanced deep submicrometer process is used. Moreover, an nMOS transistor is inserted in the discharging path of the output inverter such that the modified domino logic can be properly applied in a pipeline structure to reduce the power consumption. The addition of two 8-bit binary operands is executed in two cycles. Not only is it proven to be also suitable for long adders, the dynamic power consumption is also drastically reduced by more than 10% by the measurement results on silicon.

A Linear LDO Regulator with Modified NMCF Frequency Compensation Independent of Off-chip Capacitor and ESR

This paper presents a novel compensation design for regulators, i.e., modified NMCF (nested Miller compensation with feedforward Gm stage), resulting in a linear LDO (low dropout) regulator whose performance is independent of the off-chip capacitor and its ESR (equivalent series resistor). The proposed compensation method ensures the stability of the feedback loop and the sufficient phase margin of the LDO regulator. Besides, the transient response is fastened. The analysis of the stability is derived to solidify the proposed design. The proposed design is implemented using TSMC 0.35 mum 2P4M CMOS process. The results verify the performance and the stability on silicon. The power supply rejection ratio is 25 dB @ [200 Hz, 3 MHz], [50ft, 500ft] provided that the input voltage varies from 4 V to 5 V

A high performance current-balancing instrumentation amplifier for ECG monitoring systems

A high command-mode rejection ratio (CMRR) and low input referred noise instrumentation amplifier (IA) is presented for ECG applications. A high pass filter (HPF) with a small-Gm OTA using a current division technique is employed to attain small transconductance, which needs only a small capacitor in the HPF such that the integration on silicon is highly feasible. The proposed design is carried out by TSMC (Taiwan Semiconductor Manufacturing Company) standard 0.18 μm CMOS technology. CMRR is found to be 127 dB and input referred noise is merely 0.278 according to the simulation results.

A multiparameter implantable microstimulator SOC

Various implantable microstimulators have been proposed for clinical applications in recent years. Most of the no-battery implanted devices can be powered by a transcutaneous magnetic coupling, which basically utilizes an external transmitter coil to power and communicate with the implanted device. Small chip area and low power consumption are the keys of the implanted device. Therefore, we propose a C-less (no capacitor) area-saving ASK demodulator in this work to get rid of those large discrete capacitors required for low-frequency ASK demodulation. Additionally, a power regulator supplying a stable VDD/spl I.bar/OUT is also built in to resolve the unstable supply voltage problem resulted from the inductive link. Besides, a multiparameter control protocol which has an area advantage over microcontroller-based solutions is also proposed for various pain treatments of muscles and stimulating applications.

A low-power ADPLL using feedback DCO quarterly disabled in time domain

We propose a low-power ADPLL (all-digital phase-locked loop) using a controller which employs a binary frequency searching method in this paper. Glitch hazards and timing violations which occurred very often in the prior ADPLL designs are avoided by the control method and the modified DCO (digital-controlled oscillator) with multiplexers. Besides, the feedback DCO is disabled half a cycle in every two cycles so as to reduce 25% of dynamic power theoretically. The proposed design is implemented by only using the standard cells of a typical 0.18@mm CMOS process. The feature of power saving is verified on silicon to be merely 1.53mW at a 133MHz output.

An implantable neural interface micro-stimulator chip with external controllability

Various implantable micro-stimulators have been proposed for clinical applications in recent years. A small and flexible implanted device is the key component to any field application. This multiparameter implantable SOC (system-on-chip) chip design is aimed at neural interface stimulation, which includes controllable stimulators, and telemetry for data and power transmission. The micro-stimulator consists of 2-channel addressable current-source stimulators with seven parameters can be controlled by the external device. The external transmitter employs the RS232 format as the data transmission protocol and utilizes the NRZ code to transmit instructions and data to the implanted SOC chip. The entire SOC circuit is implemented on silicon by 0.35 /spl mu/m CMOS 2P4M technology.

A Li-ion battery charging design for biomedical implants

A Li-ion battery charging design for wireless medical implants is presented. Not only the power density is limited in the medical implants, but also the inherent lack of efficiency in a wireless powered system restricts the stability of power supply for medical implants. Therefore, a simple and power saving circuit is proposed to charge the Li-ion battery with 0.1 C. In order to resist the ripple of the voltage supplied of the carrier wave from the inducing coil, a special bias circuit to generate a bias voltage which varies with supply voltage has been designed. Moreover, the proposed design with a protection circuit can limit over-charge voltage of the Li-ion battery to prevent any damage.

A 1.7-ns ACCESS TIME SRAM USING VARIABLE BULK BIAS WORDLINE-CONTROLLED TRANSISTORS

The design of a 1.7-ns access time prototype CMOS SRAM is presented. The threshold voltages of the wordline-controlled transistors (WCT) of the proposed memory cells are dynamically variable to achieve high-speed and low-power operations. When the cell is in the read or write (R/W) mode, the VTH of the wordline-controlled transistors is pulled low by increasing the bulk bias such that the drain current will be increased. By contrast, if it is idle in a standby mode, the bulk bias will be reduced by short-circuiting to a ground voltage to subside the leakage current. The highest operating clock rate of the proposed SRAM is measured to be 667 MHz. Moreover, the proposed memory cell possess high stability, the static noise margin is close to 635 mV given the worst case (75°C, FF model, VDD = 1.6 V).

An Implantable SOC Chip for Micro-stimulating and Neural Signal Recording

An implantable SOC chip for micro-stimulation and neural signal recording is presented. This work possesses a multi-parameter control protocol to provide different stimulation waveforms, for various pain treatments of muscles and stimulating applications. Additionally, the proposed SOC chip supports several transmission rates of RS232, which in turn provides a flexibility to be integrated in a variety of different applications. Moreover, an IA (instrument amplifier) with CMRR of 120 dB and the stopband attenuation of 38 dB/dec is employed, which is capable of sensing very low voltage (1 to 10 muV) neural signal. The proposed design is implemented using TSMC 2P4M 0.35 mum CMOS process