Yin Huaxiang

An effective work-function tuning method of nMOSCAP with high-k/metal gate by TiN/TaN double-layer stack thickness

We evaluated the TiN/TaN/TiAl triple-layer to modulate the effective work function (EWF) of a metal gate stack for the n-type metal-oxide-semiconductor (NMOS) devices application by varying the TiN/TaN thick- ness. In this paper, the effective work function of EWF ranges from 4.22 to 4.56 eV with different thicknesses of TiN and TaN. The thinner TiN and/or thinner in situ TaN capping, the closer to conduction band of silicon the EWF is, which is appropriate for 2-D planar NMOS. Mid-gap work function behavior is observed with thicker TiN, thicker in situ TaN capping, indicating a strong potential candidate of metal gate material for replacement gate processed three-dimensional devices such as FIN shaped field effect transistors. The physical understandings of the sensitivity of EWF to TiN and TaN thickness are proposed. The thicker TiN prevents the Al diffusion then induces the EWF to shift to mid-gap. However, the TaN plays a different role in effective work function tuning from TiN, due to the Ta-O dipoles formed at the interface between the metal gate and the high-k layer.

The effects of process condition of top-TiN and TaN thickness on the effective work function of MOSCAP with high-k/metal gate stacks

We introduced a TaN/TiAl/top-TiN triple-layer to modulate the effective work function of a TiN-based metal gate stack by varying the TaN thickness and top-TiN technology process. The results show that a thinner TaN and PVD-process top-TiN capping provide smaller effective work function (EWF), and a thicker TaN and ALD-process top-TiN capping provides a larger EWF; here, the EWF shifts are from 4.25 to 4.56 eV. A physical understanding of the dependence of the EWF on the top-TiN technology process and TaN thickness is proposed. Compared with PVD-TiN room temperature process, the ALD-TiN 400 °C process provides more thermal budget. It would also promote more Al atoms to diffuse into the top-TiN rather than the bottom-TiN. Meanwhile, the thicker TaN prevents the Al atoms diffusing into the bottom-TiN. These facts induce the EWF to increase.

A high performance HfSiON/TaN NMOSFET fabricated using a gate-last process

A gate-last process for fabricating HfSiON/TaN n-channel metal-oxide-semiconductor-field-effect transistors (NMOSFETs) is presented. In the process, a HfSiON gate dielectric with an equivalent oxide thickness of 10 A was prepared by a simple physical vapor deposition method. Poly-Si was deposited on the HfSiON gate dielectric as a dummy gate. After the source/drain formation, the poly-Si dummy gate was removed by tetramethylammonium hydroxide (TMAH) wet-etching and replaced by a TaN metal gate. Because the metal gate was formed after the ion-implant doping activation process, the effects of the high temperature process on the metal gate were avoided. The fabricated device exhibits good electrical characteristics, including good driving ability and excellent sub-threshold characteristics. The devices gate length is 73 nm, the driving current is 117 μA/μm under power supply voltages of VGS = VDS = 1.5 V and the off-state current is only 4.4 nA/μm. The lower effective work function of TaN on HfSiON gives the device a suitable threshold voltage (~ 0.24 V) for high performance NMOSFETs. The devices excellent performance indicates that this novel gate-last process is practical for fabricating high performance MOSFETs.

Structure design and film process optimization for metal-gate stress in 20 nm nMOS devices

The optimizations to metal gate structure and film process were extensively investigated for great metal-gate stress (MGS) in 20 nm high-k/metal-gate-last (HK/MG-last) nMOS devices. The characteristics of advanced MGS technologies on device performances were studied through a process and device simulation by TCAD tools. The metal gate electrode with different stress values (0 to −6 GPa) was implemented in the device simulation along with other traditional process-induced-strain (PIS) technologies like e-SiC and nitride capping layer. The MGS demonstrated a great enhancing effect on channel carriers transporting in the device as device pitch scaling down. In addition, the novel structure for a tilted gate electrode was proposed and relationships between the tilt angle and channel stress were investigated. Also with a new method of fully stressed replacement metal gate (FSRMG) and using plane-shape-HfO to substitute U-shape-HfO, the effect of MGS was improved. For greater film stress in the metal gate, the process conditions for physical vapor deposition (PVD) TiNx were optimized. The maximum compressive stress of −6.5 GPa TiNx was achieved with thinner film and greater RF power as well as about 6 sccm N ratio.

Characterization of HfSiAlON/MoAlN PMOSFETs Fabricated by Using a Novel Gate-Last Process

We fabricate p-channel metal-oxide-semiconductor-field-effect-transistors (PMOSFETs) with a HfSiAlON/MoAlN gate stack using a novel and practical gate-last process. In the process, SiO2/poly-Si is adopted as the dummy gate stack and replaced by an HfSiAlON/MoAlN gate stack after source/drain formation. Because of the high-k/metal-gate stack formation after the 1000°C source/drain ion-implant doping activation, the fabricated PMOSFET has good electrical characteristics. The devices saturation driving current is 2.71 × 10−4 A/μm (VGS = VDS = −1.5 V) and the off-state current is 2.78 × 10−9 A/μm. The subthreshold slope of 105 mV/dec (VDS = −1.5 V), drain induced barrier lowering of 80 mV/V and Vth of −0.3 V are obtained. The research indicates that the present PMOSFET could be a solution for high performance PMOSFET applications.

High performance 70 nm CMOS device and key technologies

The fabrication of the high performance 70 nm CMOS device has been successfully explored. Some innovation technologies such as 3 nm nitrided gate oxide, dual poly-Si gate electrode, lateral local super-steep retrograde channel doping using heavy ion implantation, Ge PAI plus LEI forming 40 nm ultra-shallow S/D extension, thin and low resistance Ti-salicide and Co/Ti-salicide etc. are investigated. By these innovations in technologies, high performance 70 nm CMOS devices with excellent SCE and good driving ability have been fabricated successfully. The 57 stage unloaded 100 nm CMOS ring oscillator circuits exhibiting delay 23.8 ps/stage at 1.5 V, and 17.5 ps/stage and 12.5 ps/stage at 2 V and 3 V respectively are achieved.

Design considerations of the sub-50 nm self-aligned double gate MOSFET with a new channel doping profile

Presents a consideration to design a sub-50 nm self-aligned double gate MOSFET for fabrication by the theoretical analysis, 3D device simulation and process consideration. The scaling limits of gate length are decided by various elements which are analyzed. The optimization of the DG device structure parameters, such as thickness of Si film and spacer insulator is also illustrated. Meanwhile, we propose a new type of channel doping profile design, called SCD, whose advantages over other ways are discussed in detail. The balance between the volume inversion operation mode and the control of V/sub th/ in the DG MOSFET is achieved.