Ying-Hsin Lu

On the Origin of Anomalous Off–Current Under Hot Carrier Stress in p-Channel DDDMOS Transistors With STI Structure

This letter investigates the abnormal off-current behavior induced by hot carrier stress (HCS) in p-channel double diffused drain metal-oxide-semiconductor transistors with a shallow trench isolation (STI) structure. According to ISE-TCAD simulation, the electric field at the drain-side corners of the high-voltage n-well (HVNW) adjacent to the STI trench is stronger than the electric field in the channel center in width direction. Moreover, because a nitride layer acts as a buffer in STI, the electrons generated by impact ionization at the corners of the HVNW can be easily trapped in the nitride layer or at the liner oxide/nitride layer interface. Furthermore, the extension of electron trapping in STI from drain to source during HCS forms the off-current conductive path. Based on the charge pumping measurements at different operation conditions, this path formation is further demonstrated by the comparisons of charge pumping measurements between initial state and after HCS.

Investigation of abnormal negative threshold voltage shift under positive bias stress in input/output n-channel metal-oxide-semiconductor field-effect transistors with TiN/HfO2 structure using fast I-V measurement

This letter investigates abnormal negative threshold voltage shifts under positive bias stress in input/output (I/O) TiN/HfO2 n-channel metal-oxide-semiconductor field-effect transistors using fast I-V measurement. This phenomenon is attributed to a reversible charge/discharge effect in pre-existing bulk traps. Moreover, in standard performance devices, threshold-voltage (Vt) shifts positively during fast I-V double sweep measurement. However, in I/O devices, Vt shifts negatively since electrons escape from bulk traps to metal gate rather than channel electrons injecting to bulk traps. Consequently, decreasing pre-existing bulk traps in I/O devices, which can be achieved by adopting HfxZr1−xO2 as gate oxide, can reduce the charge/discharge effect.

High-k shallow traps observed by charge pumping with varying discharging times

In this paper, we investigate the influence of falling time and base level time on high-k bulk shallow traps measured by charge pumping technique in n-channel metal-oxide-semiconductor field-effect transistors with HfO2/metal gate stacks. NT-Vhigh level characteristic curves with different duty ratios indicate that the electron detrapping time dominates the value of NT for extra contribution of Icp traps. NT is the number of traps, and Icp is charge pumping current. By fitting discharge formula at different temperatures, the results show that extra contribution of Icp traps at high voltage are in fact high-k bulk shallow traps. This is also verified through a comparison of different interlayer thicknesses and different TixN1−x metal gate concentrations. Next, NT-Vhigh level characteristic curves with different falling times (tfalling time) and base level times (tbase level) show that extra contribution of Icp traps decrease with an increase in tfalling time. By fitting discharge formula for different tfal...

Electron-electron scattering-induced channel hot electron injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors with high-k/metal gate stacks

This work investigates electron-electron scattering (EES)-induced channel hot electron (CHE) injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors (n-MOSFETs) with high-k/metal gate stacks. Many groups have proposed new models (i.e., single-particle and multiple-particle process) to well explain the hot carrier degradation in nanoscale devices and all mechanisms focused on Si-H bond dissociation at the Si/SiO2 interface. However, for high-k dielectric devices, experiment results show that the channel hot carrier trapping in the pre-existing high-k bulk defects is the main degradation mechanism. Therefore, we propose a model of EES-induced CHE injection to illustrate the trapping-dominant mechanism in nanoscale n-MOSFETs with high-k/metal gate stacks.

Trap state passivation improved hot-carrier instability by zirconium-doping in hafnium oxide in a nanoscale n-metal-oxide semiconductor-field effect transistors with high-k/metal gate

This work investigates the effect on hot carrier degradation (HCD) of doping zirconium into the hafnium oxide high-k layer in the nanoscale high-k/metal gate n-channel metal-oxide-semiconductor field-effect-transistors. Previous n-metal-oxide semiconductor-field effect transistor studies demonstrated that zirconium-doped hafnium oxide reduces charge trapping and improves positive bias temperature instability. In this work, a clear reduction in HCD is observed with zirconium-doped hafnium oxide because channel hot electron (CHE) trapping in pre-existing high-k bulk defects is the main degradation mechanism. However, this reduced HCD became ineffective at ultra-low temperature, since CHE traps in the deeper bulk defects at ultra-low temperature, while zirconium-doping only passivates shallow bulk defects.

The Impact of Different TiN Capping Metal Thicknesses on High-k Oxygen Vacancies in n-MOSFETs

This letter investigates the impact of two different TiN capping metal thicknesses on high-k oxygen vacancies in n-MOSFETs. Traditionally, oxygen vacancies in HfO2 can be repaired by nitrogen in the TiN gate, and these repairs become more pronounced as thickness increases. Nevertheless, in this letter, where the thicknesses of the TiN capping metal was less than 30 Å, more oxygen vacancies were found in thick-capped devices than in the thin-capped devices because the repair of oxygen vacancies is dominated by the diffusion of oxygen rather than by the diffusion of nitrogen.

Analysis of Contrasting Degradation Behaviors in Channel and Drift Regions Under Hot Carrier Stress in PDSOI LD N-Channel MOSFETs

This letter studies the effects of hot carrier stress (HCS) in laterally diffused silicon-on-insulator n-channel metal–oxide–semiconductor field-effect transistors. After HCS, threshold voltage and subthreshold swing degrade, while the ON-state current exhibits degradation after an abnormal spike due to hole trapping in the resist-protective oxide. Impact ionization simulation shows that low doping concentrations in the drift region cause a severe Kirk effect under HCS and more severe degradation at higher gate voltages. However, degradation in the channel contrasts with the simulation result, which suggests an additional mechanism. Variable temperature HCS confirms that channel degradation is instead dominated by temperature.

Abnormal Recovery Phenomenon Induced by Hole Injection During Hot Carrier Degradation in SOI n-MOSFETs

This letter investigates an abnormal recovery phenomenon induced by hole injection during hot carrier degradation in silicon-on-insulator n-type metal–oxide–semiconductor transistors. The method by which the hole injection induces the abnormal recovery behavior can be clarified by different hot carrier degradation (HCD) measurement sequences. According to this HCD result, the channel surface energy band is drawn down and the interface defect will be temporarily shielded, an effect caused by the trapped hole. Furthermore, results of different stress voltage experiments indicate that the amount of hole injection is determined by the electric field between the gate and drain.

Investigation of abnormal off-current in p-channel double diffused drain metal-oxide-semiconductor transistors after hot carrier stress

This paper studies the degradation behaviors in IV characteristics and the corresponding improvement for p-channel double diffused drain metal-oxide-semiconductor (DDDMOS) transistors after hot carrier stress (HCS). There is an apparent current which is flowed from source to drain in the off-region after HCS. According to the IV characteristic comparisons between different device structures and ISE-TCAD simulation results, the location and mechanism of this abnormal off-current can be demonstrated. Furthermore, this off-current is suppressed effectively by the different process flows in STI fabrication for this DDDMOS device.

Analysis of Oxide Trap Characteristics by Random Telegraph Signals in nMOSFETs With HfO 2 -Based Gate Dielectrics

This letter investigates the oxide trap properties in n-channel metal-oxide-semiconductor field-effect transistors with HfO₂ and Hf_1-xZr_xO₂/metal gate-stacks by an analysis of random telegraph signals. According to the multiphonon emission theory, the extracted relaxation energies show gate voltage dependence in devices with HfO₂-based stacks. This dependence results from the different strengths of vibrations of the nearest neighbor Hf atoms of the oxygen vacancy in the immediate vicinity of the oxide trap. Furthermore, this dependence also induces an abnormal gate voltage dependence in terms of the activation energy required for electron capture. These results are confirmed by comparisons between two HfO₂-based devices (HfO₂ and Hf_1-xZr_xO₂).