Ying Yu Chen

A SPICE-compatible model of graphene nano-ribbon field-effect transistors enabling circuit-level delay and power analysis under process variation

This paper presents the first parameterized, SPICE-compatible compact model of a Graphene Nano-Ribbon Field-Effect Transistor (GNRFET) with doped reservoirs that also supports process variation. The current and charge models closely match numerical TCAD simulations. In addition, process variation in transistor dimension, edge roughness, and doping level in the reservoir are accurately modeled. Our model provides a means to analyze delay and power of graphene-based circuits under process variation, and offers design and fabrication insights for graphene circuits in the future. We show that edge roughness severely degrades the advantages of GNRFET circuits; however, GNRFET is still a good candidate for low-power applications.

Clock tree synthesis under aggressive buffer insertion

In this paper, we propose a maze-routing-based clock tree routing algorithm integrated with buffer insertion, buffer sizing and topology generation that is able to consider general buffer insertion locations in order to achieve robust slew control. Buffer insertion along routing paths had been mostly avoided previously due to the difficulty to maintain low skew under such aggressive buffer insertion. We develop accurate timing analysis engine for delay and slew estimation and a balanced routing scheme for better skew reduction during clock tree synthesis. As a result, we can perform aggressive buffer insertion with buffer sizing and maintain accurate delay information and low skew. Experiments show that our synthesis results not only honor the hard slew constraints but also maintain reasonable skew.

Schottky-barrier-type Graphene Nano-Ribbon Field-Effect Transistors: A study on compact modeling, process variation, and circuit performance

Graphene Nano-Ribbon Field-Effect Transistors (GNR-FETs) have emerged as promising next-generation devices. In particular, Schottky-barrier-type GNRFETs (SB-GNRFETs) have piqued interest due to their ambipolar I-V characteristics. Despite manufacturing successes, the lack of a SPICE-compatible compact model of SB-GNRFETs has hindered studies on evaluating the performance of this emerging technology on the circuit level. In this paper, we present the first SPICE-compatible model of SB-GNRFETs that takes various design parameters into account, which not only enables circuit-level simulations, but also provides a means to evaluate process variation, including effects of channel length, transistor width, oxide thickness, and graphene-specific edge roughness. With this model, we are able to explore the design space of SB-GNRFETs, evaluate delay and power performance of SB-GNRFET circuits, and compare them with conventional Si-CMOS and Metal-Oxide-Semiconductor-(MOS-)GNRFETs. Our study shows that SB-GNRFETs have higher speed and higher power dissipation, and have lower energy delay product than both Si-CMOS and MOS-GNRFETs, while MOS-GNRFETs are potentially good for low-power applications despite the presence of graphene-metal contact resistance that are not present in SB-GNRFET circuits. Two practical factors severely degrade the performance and even affect the functionality of SB-GNRFET circuits: 1) edge roughness and 2) limitation on operating point shifting.

Highly accurate SPICE-compatible modeling for single- and double-gate GNRFETs with studies on technology scaling

In this paper, we present a highly accurate closed-form compact model for Schottky-Barrier-type Graphene Nano-Ribbon Field-Effect Transistors (SB-GNRFETs). This is a physics-based analytical model for the current-voltage (I-V) characteristics of SB-GNRFETs. We carry out accurate approximations of Schottky barrier tunneling, channel charge and current, which provide improved accuracy while maintaining compactness. This SPICE-compatible compact model surpasses the existing model [15] in accuracy, and enables efficient circuit-level simulations of futuristic GNRFET-based circuits. The proposed model considers various design parameters and process variation effects, including graphene-specific edge roughness, which allows complete and thorough exploration and evaluation of SB-GNRFET circuits. We are able to model both single- and double-gate SB-GNRFETs, so we can evaluate and compare these two types of SB-GNRFET. We also compare circuit-level performance of SB-GNRFETs with multi-gate (MG) Si-CMOS for a scalability study in future generation technology. Our circuit simulations indicate that SB-GNRFET has an energy-delay product (EDP) advantage over Si-CMOS; the EDP of the ideal SB-GNRFET (assuming no process variation) is ~1.3% of that of Si-CMOS, while the EDP of the non-ideal case with process variation is 136% of that of Si-CMOS. Finally, we study technology scaling with SB-GNRFET and MG Si-CMOS. We show that the EDP of ideal (non-ideal) SB-GNRFET is ~0.88% (54%) EDP of that of Si-CMOS as the technology nodes scales down to 7 nm.

Graphene nano-ribbon field-effect transistors as future low-power devices

The graphene nano-ribbon field effect transistor (GNRFET) is an emerging technology that received much attention in recent years. Recent work on GNRFET circuit simulations has shown that GNRFETs may have potential in low power applications. In this paper, we review the existing work on GNRFET circuit modeling, compare the two varieties of GNRFETs, Metal-Oxide-Semiconducting-(MOS-)type and Schottky-Barrier-(SB-)type GNRFETs, and thoroughly discuss and explore their respective strengths in terms of delay, power, and noise margin. From this point of view, we discuss their possible applications, especially the use towards low-power computing. Our simulations show that ideal (nonideal) MOS-GNRFET consumes 18% (35%) and 54% (102%) total power as compared to high-performance (HP) Si-CMOS and low-power (LP) Si-CMOS, respectively. SB-GNRFET does not compare favorably to MOS-GNRFET in terms of power consumption. However, ideal (non-ideal) SB-GNRFET has 3% (5.4X) and 0.45% (83.5%) energy-delay product (EDP) compared to Si-CMOS (HP) and Si-CMOS (LP), respectively, while ideal (non-ideal) MOS-GNRFET has 8% (93%) and 1.25% (14.3%) EDP compared to Si-CMOS (HP) and Si-CMOS (LP), respectively.

Analytical SPICE-Compatible Model of Schottky-Barrier-Type GNRFETs With Performance Analysis

This paper presents an accurate analytical compact model for Schottky-barrier-type graphene nanoribbon field-effect transistors (SB-GNRFETs). This is a physics-based analytical model for the current-voltage (I-V) characteristics of SB-GNRFETs. The proposed model considers various design parameters and process variation effects, including graphene-specific line-edge roughness, which allows thorough exploration and evaluation of SB-GNRFET circuits. We develop accurate approximations of SB tunneling, channel charge, and current, which provide accurate results while maintaining model compactness. We evaluate the effect of design parameters and process variations on the performance of SB-GNRFETs. We also compare circuit-level performance of SB-GNRFETs with multigate (MG) Si-CMOS (e.g., FinFETs). Our circuit simulations indicate that SB-GNRFET has an energy-delay product (EDP) advantage over Si-CMOS, although GNR-specific process variation, especially the line-edge roughness, would significantly downgrade such an advantage; the EDP of the ideal SB-GNRFET (assuming no process variation) is ~2.5% of that of Si-CMOS, while the EDP of the nonideal case with process variation is ~68% of that of Si-CMOS. Finally, we study technology scaling with SB-GNRFET and MG Si-CMOS. We show that the EDP of ideal (nonideal) SB-GNRFET is ~0.88% (54%) EDP of that of Si-CMOS as the technology nodes scale down to 7 nm.

A SPICE-Compatible Model of MOS-Type Graphene Nano-Ribbon Field-Effect Transistors Enabling Gate- and Circuit-Level Delay and Power Analysis Under Process Variation

This paper presents the first parameterized SPICE-compatible compact model of a graphene nano-ribbon field-effect transistor (GNRFET) with doped reservoirs, also known as MOS-type GNRFET. The current and charge models closely match numerical TCAD simulations. In addition, process variation in transistor dimension, line edge roughness, and doping level in the reservoirs are accurately modeled. Our model provides a means to analyze delay and power of graphene-based circuits under process variation, and offers design and fabrication insights for graphene circuits in the future. We show that line edge roughness severely degrades the advantages of GNRFET circuits; however, GNRFET is still a good candidate for low-power applications.

Flexible transition metal dichalcogenide field-effect transistors: A circuit-level simulation study of delay and power under bending, process variation, and scaling

In this paper, a new and efficient SPICE model of flexible transition metal dichalcogenide field-effect transistors (TMDFETs) is developed for different types of materials, considering effects when scaling the transistor size down to the 16-nm technology node. Extensive circuit-level simulations are performed using this model, and the delay and power performance of TMDFET circuits with different amounts of bending are reported. Simulation results indicate that delay and power tradeoff can be done in TMDFET circuits via bending. Effects from process variation are also evaluated via circuit simulations. Finally, our cross-technology and scaling studies show that while TMDFETs perform better than Si-based transistors in terms of energy-delay product (EDP) at 180-nm and 90-nm technology nodes (the best being 12.7% and 40.7% of that of Si-based transistors, respectively), their EDPs are worse than Si-based transistors (at least 4.9× of that of the best performing Si-based transistor) on the 16-nm technology node. Such a compact model would enable SPICE-level circuit simulation for early assessment, design, and evaluation of futuristic TMDFET-based flexible circuits targeting advanced technology nodes.

A SPICE model of flexible transition metal dichalcogenide field-effect transistors

This paper presents the first SPICE model of the transition metal dichalcogenide (TMD) field-effect transistor (FET), which is a promising candidate for flexible electronics. The model supports different transistor design parameters such as width, length, oxide thickness, and various channel materials (MoS2, WSe2, etc.), as well as the applied strain, which enables the evaluation of transistor- and circuit-level behavior under process variation and different levels of bending. We performed SPICE simulations on digital logic gates to explore the design space of both MoS2- and WSe2-based transistors, and to evaluate the projected performance of these circuits under applied strain. Our simulations show that WSe2 circuits outperform MoS2 and Si-based CMOS in terms of energy-delay product (EDP) by up to 1 order of magnitude, depending on applications. Finally, we investigate TMDFETs behavior under process variation.

Compact Modeling to Device- and Circuit-Level Evaluation of Flexible TMD Field-Effect Transistors

In this paper, a compact SPICE model of flexible transition metal dichalcogenide field-effect transistors (TMDFETs) is developed with considering effects when scaling the transistor size down to the 10-nm technology node. The model supports different transistor design parameters such as width, length, oxide thickness, and various channel materials, as well as the applied strain, which enables the evaluation of transistor- and circuit-level behavior under process variation and different levels of bending. Extensive device-level simulations are performed using this model, and TMDFETs are compared with different Si- and graphene-based devices. We performed circuit-level simulations, and reported the delay, power, and EDP of the benchmark circuits. Effects from process variation are also evaluated. These cross-technology studies show that TMDFET’s power is comparable to the low-power multigate devices (about 0.4% lower). The delay and EDP are 60% and 2.3% higher than the graphene-based devices, respectively. The developed compact model would enable SPICE-level circuit simulation for early assessment, design, and evaluation of futuristic TMDFET-based flexible circuits targeting advanced technology nodes.