Huaguo Liang

A scheme of test data compression based on coding of even bits marking and selective output inversion

A new scheme of test data compression/decompression, namely coding of even bits marking and selective output inversion, is presented. It first uses a special kind of codewords, odd bits of which are used to represent the length of runs and even bits of which are used to represent whether the codewords finish. The characteristic of the codewords make the structure of decompressor simple. It then introduces a structure of selective output inversion to increase the probability of 0s. This scheme can obtain a better compression ratio than some already known schemes, but it only needs a very low hardware overhead. The performance of the scheme is experimentally confirmed on the larger examples of the ISCAS89 benchmark circuits.

A BIST Scheme Based on Selecting State Generation of Folding Counters

In this paper, a BIST scheme based on selecting state generation of folding counters is presented. LFSR is used to encode the seeds of the folding counters, where folding distances (or indexes) are stored to control deterministic test patterns generation, so that the generated test set is completely equal to the original test set. This scheme solves compression of the deterministic test set and overcomes overlapping and redundancy of test patterns produced by the different seeds. Experimental results prove that it not only achieves higher test data compression ratio, but also efficiently reduces test application time, and that the average test application time is only four percent of that of the same type scheme.

Design of a Radiation Hardened Latch for Low-Power Circuits

As technology node entered the era of nanotechnology, a latch is much more susceptible to soft errors caused by energetic particles in space radiation environment. In order to enhance the Single Event Upset (SEU) -tolerance capability of a latch, this paper presents an interlocking soft error hardened latch (ISEHL) which is suitable for low-power circuits. The proposed latch is based on three C-elements which are errors tolerable, and the logic state of each C-element is determined by the output state of two other C-elements, which constitute an interlocking soft error hardened latch. The simulation results show that the proposed ISEHL latch can not only be applied to clock-gating circuits but also perform with 41% power as well as 95% Power Delay Product (PDP) saving as comparing with the FERST latch which performs an equivalent superior SEU-tolerance ability.

Sharing BIST with multiple cores for system-on-a-chip

A novel architecture based on mixed mode BIST for sharing among multiple logic cores on an system-on-a-chip is presented. In the architecture a single-polynomial LFSR with maximum degree in the multiple cores can be selected to generate pseudo-random patterns to cover the easy to detect faults for the all cores. For the remaining faults of the each core deterministic test patterns can be compressed by a two-dimensional compression scheme, where the LFSR encodes the seeds of a folding counter as the seeds of the LFSR so as to reduce amount of test data storage, and all of the cores under test can use the unique LFSR to decompress the encoded seeds. Experimental results indicate that the proposed scheme can achieve a significant amount of compression for test data storage, and the simple and flexible architecture can be directly embedded on chip for systems-on-a-chip test.

Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology

This brief presents a double-node-upset-resilient latch (DNURL) design in 22-nm CMOS technology. The latch comprises three interlocked single-node-upset-resilient cells and each of the cells mainly consists of three mutually feeding back Muller C-elements. Simulation results demonstrate the double-node upset resilience and a 73.0% delay-power-area product saving on average compared with the up-to-date DNURL designs.

A Methodology for Characterization of SET Propagation in SRAM-Based FPGAs

This paper presents a methodology for accurate characterization of Single Event Transient (SET) propagation in SRAM-based Field Programmable Gate Arrays (FPGAs): both generation and measurement of SETs are implemented on chip, respectively connected to input port and output port of the test combinational paths. The scheme we developed is mainly based on two circuits: 1) the one is a SET generating circuit for on-chip producing an adjustable pulse with a temporal resolution of near 100 ps; 2) the other is a SET measuring circuit for on-chip measuring pulses with a temporal resolution of near 80 ps and the ability to detect narrow transient pulses of about 300 ps. Based on above methodology, we investigate the effect of traversing seven logic chains with different gate types and multiple chain lengths on pulse widths, i.e., Propagation Induced Pulse Distorting (PIPD). Results demonstrate, when SETs propagate along Look Up Tables (LUTs) in Virtex-6 FPGAs, there is a broadening for negative SETs (1-0-1) while not for positive SETs (0-1-0); in addition, pulse width has no impact on PIPD, and which is linearly proportional to the number of stages.

A transient pulse dually filterable and online self-recoverable latch

This paper presents a transient Pulse Dually Filterable and online Self-Recoverable (referred to as PDFSR) latch. Based on soft error masking property of C-element and using built-in delayed paths combined with a Schmitt inverter, a single event transient (SET) pulse could be dually filtered. Meanwhile, mutually feeding back mechanism of multiple C-elements was constructed to retain data, which makes the latch self-recoverable from a single event upset (SEU). Simulation results have demonstrated the SET filtering ability and SEU resilience at the cost of only 2.0% area-powerdelay-width product increase on average, compared with the similar latches.

A low-leakage and NBTI-mitigated N-type domino logic

NBTI-induced transistor aging has become a prominent factor affecting the reliability of circuits. Reducing leakage consumption is one of the major design goals. Domino logic circuits are applied extensively in high-performance integrated circuits. A circuit technique for mitigating NBTI-induced degradation and reduce standby leakage current is presented in this paper. Two transistors are added to the standard domino circuit to pull both the dynamic node and the output up to VDD, which puts both the keeper and the inverter pMOS transistor into recovery mode in standby mode. Due to the stack effect, leakage current is reduced by the all-0 input vector and the added transistors. Experimental results reveal up to 33% NBTI-induced degradation reduction and up to 79% leakage current reduction.

A dynamic self-adaptive correction method for error resilient application

The aggressive scaling down technology has posed transistor aging to be a new challenging to the reliability of circuits. Transistor aging could cause the gradual degradation of circuit performance and eventually lead to timing error. In this paper, a dynamic self-adaptive method is proposed to protect the circuit from the influence of transistor aging. This makes use of aging detection sensors and self-adaptive clock scaling cell. Aging sensors would automatically wake up the clock scaling cell to shift the clock phase of circuits when an error occurs. Then the timing error would be masked by a second sampling with the shifted clock. The method is simulated by Hspice using 65nm technology. The evaluation results show that this method is effective to error resilient with no impact on normal function of circuits, and it improves the MTTF by 1.16 times with 22.73% circuit overheads on average when the phase difference is 20% clock cycle.

An improved communication scheme for non-HOL-blocking wireless NoC

Abstract As the wireless interface often requires handling numbers of data simultaneously in wireless network-on-chip, it potentially causes data congestions. The degradation of wireless data transfer can tremendously reduce the efficiency of the network communication. In this paper, virtual output queuing (VOQ) technique has been used to eliminate the head-of-line blocking issue. Moreover, a novel and effective communication scheme has also been introduced to alleviate the traffic load in wireless nodes and hence improving the efficiency of wireless communication. Simulation results indicate that our proposed architecture is advantageous in various aspects including the transfer latency, network throughput and energy consumption.