Zuying Luo

Area minimization of power distribution network using efficient nonlinear programming techniques

This paper deals with area minimization of power network for very large-scale integration designs. A new algorithm based on efficient nonlinear programming techniques is presented to solve this problem. During the optimization, a penalty method, conjugate gradient method, circuit sensitivity analysis, and merging adjoint networks are applied, which enables the algorithm to optimize large circuits. The experiment results prove that this algorithm is robust and can achieve the objective of minimizing the area of power network in a short runtime.

A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery

In this paper, we present an efficient method to budget on-chip decoupling capacitors (decaps) to optimize power delivery networks in an area efficient way. Our algorithm is based on an efficient gradient-based non-linear programming method for searching the solution. Our contributions are an efficient gradient computation method (time-domain merged adjoint network) and a novel equivalent circuit modeling technique to speed up the optimization process. Experimental results demonstrate that the algorithm is capable of efficiently optimizing very large scale P/G networks.

VLSI on-chip power/ground network optimization considering decap leakage currents

In todays power/ground (P/G) network design, on-chip decoupling capacitors(decaps) are usually made of MOS transistors with source and drain connected together. The gate leakage current becomes worse as the gate oxide layer thickness continues to shrink below 20/spl Aring/. As a result, decaps become leaky due to the gate leakage from CMOS devices. In this paper, we take a first look at the leaky decaps in P/G network optimization. We propose a leakage current model for practical decaps and also present a new two-stage leakage-current-aware approach to efficiently optimize P/G networks in a more area efficient way.

Partial random walk for large linear network analysis

This paper proposes a new simulation algorithm for analyzing large power distribution networks, modelled as linear RLC circuits, based on a partial random walk concept. The random walk simulation method has been shown to be an efficient way to solve for a small number of nodes in a larger power distribution network by H.-F. Qian et al. (2003), but the algorithm becomes expensive to solve for nodes that are more than a few. We combine direct methods like LU factorization with the random walk concept to solve power distribution networks when a significant number of node waveforms is required. We also apply an equivalent circuit modelling method to speed up the direct simulation of subcircuits. Experimental results show that the resulting algorithm, called partial random walk (PRW), has significant advantages over the pure random walk method especially when the VDD/GND nodes are sparse and accuracy requirement is high.

Transient analysis of on-chip power distribution networks using equivalent circuit modeling

This paper presents an efficient method to analyze power distribution networks in the time-domain. Instead of directly analyzing the integration approximated power/ground networks at each time step as previous methods did, the new method first builds the equivalent models for many series RLC-current chains based on their Nortons form companion models in the original networks, and then the precondition conjugate gradient (PCG) based iterative method is used to solve the reduced networks. The solutions of the original networks then are back solved from that of the reduced networks. Our contribution is the introduction of an efficiency algorithm for reducing RLC power/ground network complexities by exploitation of the regularities in the power/ground networks. Experimental results show that the complexities of reduced networks are typically significantly smaller than that of the original circuits, which makes the new algorithm extremely fast. For instance, power/ground networks with more than one million branches can be solved in a few minutes on modern Sun workstations.

Time-domain analysis methodology for large-scale RLC circuits and its applications

With soaring work frequency and decreasing feature sizes, VLSI circuits with RLC parasitic components are more like analog circuits and should be carefully analyzed in physical design. However, the number of extracted RLC components is typically too large to be analyzed efficiently by using present analog circuit simulators like SPICE. In order to speedup the simulations without error penalty, this paper proposes a novel methodology to compress the time-descritized circuits resulted from numerical integration approximation at every time step. The main contribution of the methodology is the efficient structure-level compression of DC circuits containing many current sources, which is an important complement to present circuit analysis theory. The methodology consists of the following parts: 1) An approach is proposed to delete all intermediate nodes of RL branches. 2) An efficient approach is proposed to compress and back-solve parallel and serial branches so that it is error-free and of linear complexity to analyze circuits of tree topology. 3) The Y to π transformation method is used to error-free reduce and back-solve the intermediate nodes of ladder circuits with the linear complexity. Thus, the whole simulation method is very accurate and of linear complexity to analyze circuits of chain topology. Based on the methodology, we propose several novel algorithms for efficiently solving RLC-model transient power/ground (P/G) networks. Among them, EQU-ADI algorithm of linear-complexity is proposed to solve RLC P/G networks with mesh-tree or mesh-chain topologies. Experimental results show that the proposed method is at least two orders of magnitude faster than SPICE while it can scale linearly in both time-and memory-complexity to solve very large P/G networks.

Localized statistical 3D thermal analysis considering Electro-Thermal coupling

In this paper, we propose a novel method for analyzing fewer hot spots in a chip. The method, called SNSOR (Single-Node Successive Over Relaxation), is based on a novel localized relaxed iterative approach to perform statistical analysis on one hot spot at a time. Based on SNSOR, we propose an approximation method, called ET-SNSOR (Electro-Thermal SNSOR), to deal with the electro-thermal coupling (ETC) effects. ET-SNSOR first uses the iterative method to update correlations from ETC, and then computes standard temperature deviations for hot spots, according to ETC and updated correlations. Experiments show that ET-SNSOR is three orders of magnitude faster than the Monte-Carlo method with small errors (less than 4.76% on maximum). It only takes an average of 0.18 second to analyze one hot spot statistically for a large test case of 1.3M nodes with ETC effects.

Statistic Analysis of Power/Ground Networks Using Single-Node SOR Method

In this paper, we propose an efficient statistical analysis method for analyzing on-chip power grids. The new method, called SN-SOR (and its faster version, PSN- SOR), is based on a novel localized relaxed iterative approach and it can perform variational analysis on one node at a time. PSN-SOR further speeds up the analysis by using a refined conditioner, where the initial solution of SN-SOR is used as the pre-conditioner for the later iterations. Experimental results show that PSN-SOR is about two orders of magnitude(186X) faster than Monte- Carlo method with slight errors less than 5.685% on maximum and is about one order magnitude (41X) faster than general global successive over relaxation (SOR) method. PSN-SOR is more accurate and efficient than the recently proposed random walk method for localized statistical analysis.

Power/Ground Network Optimization Considering Decap Leakage Currents

In this brief, the authors take a first look at the leakage effects of decaps in power/ground (P/G) grid optimization. Through the use of an approximate leakage current model, it is revealed that simple usage of the leakage model in traditional optimization methods cannot help in reducing noises on P/G grids, and it even hurts power consumption due to overadded decaps. Therefore, it is necessary to develop an efficient method to budget decaps when leakage effect is considered. Here, a new two-stage approach to solve this problem is proposed. Experimental results demonstrate the effectiveness of our new method

Optimal wire sizing in early-stage design of on-chip power/ground (P/G) networks

Due to decreasing supply voltages and increasing power consumption of todays VLSI chips, IR drops on on-chip power/ground (P/G) grids have to be explicitly considered during the floorplanning stage in todays physical design flow. Thus, it is very important to size the P/G grids in the floorplanning to efficiently minimize the worst-case IR drop subject to limited routing resource in early-stage P/G network design. In this paper we first present the optimization problem of mesh-structured center-bumped P/G grids under given routing resources. We then propose an efficient wire sizing method based on an incomplete Cholesky conjugate gradient (ICCG) simulation method to obtain the optimal solution for mesh-structured P/G grids. After this we improve the simulation method by using a novel simulation method, named approximate current distribution (ACD), to speedup the optimization. Finally we present a closed-form expression to directly calculate the optimal sizes of P/G grids given the current distributions computed from ACD. Experimental results show that the optimization cost function has one global minimum with respect to the width ratio. The theoretically computed optimal solutions match very well with the simulated results, which can lead to significant speedup in future IR-drop aware floorplanning.