Zhangming Zhu

A 0.45-V, 14.6-nW CMOS Subthreshold Voltage Reference With No Resistors and No BJTs

We present a low-voltage low-power CMOS subthreshold voltage reference with no resistors and no bipolar junction transistors in a wide temperature range. The temperature stability is improved by second-order compensation. By employing a bulk-driven technique and the MOS transistors working in the subthreshold region, the supply voltage and the power dissipation are reduced. Moreover, a trimming circuit is adopted to compensate for the process-related reference voltage variation. The proposed voltage reference has been fabricated with the 0.18-μm 1.8-V CMOS process. The measurement results show that the minimum power supply voltage is 0.45 V, the power consumption is 14.6 nW, the average temperature coefficient measured from -40 °C to 125 °C is 63.6 ppm/°C, and the line regulation is 1.2 mV/V in the power supply voltage ranging from 0.45 to 1.8 V. In addition, the chip area is 0.012 mm2.

A 6-to-10-Bit 0.5 V-to-0.9 V Reconfigurable 2 MS/s Power Scalable SAR ADC in 0.18 CMOS

An asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for sensor applications is presented. High linear and power efficient switching scheme is proposed. The proposed low leakage latched dynamic cell in SAR logic and wide range configurable delay element extend the flexibility of speed and resolution tradeoff. The ADC fabricated in 0.18 μm CMOS process covers 6-10 bit resolution and 0.5 V-0.9 V power supply range. At 10 bit mode and 0.5 V operation, the proposed SAR ADC achieves 56.36 dB SNDR and 67.96 dB SFDR with sampling rate up to 2 MS/s, corresponding to a figure-of-merit of 20.6 fJ/conversion-step. The proposed ADC core occupies an active area of about 300×700 μm2.

A 19-nW 0.7-V CMOS Voltage Reference With No Amplifiers and No Clock Circuits

This brief provides a novel voltage reference circuit that uses four optimization techniques to effectively save power dissipation: 1) All the amplifiers have been eliminated, but two important voltages are still successfully equalized without using any amplifier; 2) the clock circuits are not required in the proposed design; 3) there is no need for extra biasing circuit; and 4) all the MOS transistors are in the subthreshold region to make the power supply voltage low. Moreover, a trimming circuit has been adopted to ensure the accuracy of the reference voltage. This novel voltage reference circuit has been fabricated with the Semiconductor Manufacturing International Corporation 0.18-μm 1.8-V CMOS process. The measurement results show that the power consumption is only 19 nW, the power supply voltage is only 700 mV, the temperature coefficient is 22.11 ppm/°C under a temperature of -25 °C-+85 °C, and the line sensitivity is as good as 571 μV/V.

A 0.5-V 1.3-

This brief presents a low-power analog acquisition front-end circuit for a Wireless Body Area Network. This front-end system mainly consists of three parts, namely, chopped capacitively coupled instrumentation amplifier (CCIA), switched capacitor filter (SC-filter), and successive-approximation analog-to-digital converter. In order to reduce the power consumption, the supply voltage is scaled to 0.5 V, and all analog building blocks are biased in the subthreshold region. The chopper-stabilized technique is introduced to eliminate the 1/f noise, and a dc-servo loop is employed in the CCIA to suppress the electrode offset. A low-power second-order SC-filter is employed to eliminate the spikes produced by the CCIA, which also realizes a tunable gain to satisfy the specification. This low-power analog front-end circuit has been fabricated in a 0.18-μW CMOS process. It occupies 1 mm2 and consumes a minimal 1.3 μW at 0.5 V. It achieves a bandwidth of 0.5-250 Hz, a CMRR of 95 dB, and an input impedance of 48 MΩ, respectively.

\mu\text{W}

Based on SMIC 0.18μm standard CMOS technology, an input-powered vibrational energy harvesting interface circuit is proposed. It can be applied in energy harvesting devices for the extremely low voltage and high conversion rate. The simulation results show that the minimum input voltage could be as low as 0.15V by utilizing bulk-driven technique. Correspondingly, the voltage conversion efficiency can reach up to 80%. And the power conversion efficiency is also 80% when voltage equals to 0.25V. The proposed input-powered interface circuit, compared with the conventional output-powered circuits, can automatically shut down when the input voltage amplitude is low enough, thereby avoiding unnecessary energy loss.

Analog Front-End CMOS Circuit

This paper proposes an asynchronous 12 × 12 -bit array multiplier. Firstly, we proposed a new asynchronous pipeline of which data processing and completion detection can be carried out simultaneously by applying multi-threshold semi-static NCL (MTSNCL) to asynchronous combinational logic. Sencondly, the pipeline is used for designing an asynchronous 12 × 12 -bit array multiplier. Finally, both the proposed array multiplier and the original array multiplier are simulated based on SMIC 0.18-µm CMOS technology. Compared with the general asynchronous array multiplier, the new array multiplier has 76.5% higher throughput, 43.8% lower TDD cycle time and 38.7% lower static power consumption. The multi-threshold array multiplier is suitable for high-speed lower-power asynchronous multiplier design.

A highly efficient interface circuit for ultra-low-voltage energy harvesting

Based on the analytical thermal model for the top layer of three-dimensional integrated circuits (3D ICs) without through silicon vias (TSVs), the corresponding analytical thermal model taking TSVs into account is proposed. TSVs density ρ and effective thermal conductivity is introduced in this paper. The simulation results show that, the temperature increases sharply with the decrease of ρ for more layers and smaller ρ, and the best range of TSVs density ρ is 0.5% to 1% for an 8-layer 3D IC. These results can be effectively used as design guidelines in 3D IC thermal management studies.

A high-speed asynchronous array multiplier based on multi-threshold semi-static NULL convention logic pipeline

The fundamental principles of the substrate bipolar transistor in CMOS technology and the bulk-driven MOSFET are discussed and analyzed. Based on the bulk-driven PMOSFET, substrate PNP transistor and current feedback technique an 0.8 V low power PTAT voltage reference is proposed for the temperature sensors applications. At a 0.8 V power supply with -25/spl sim/130 /spl deg/C temperature range, the temperature coefficient of voltage reference is 0.926 mV/K, and the supply current is about 4.5 /spl mu/V. When the power supply ranged 0.7 V/spl sim/1.0 V, the voltage reference is about 302 mV in the room temperature. The active area of reference is about 0.01 mm/sup 2/.

A thermal model for the top layer of 3D integrated circuits considering through silicon vias

Accurate analytical models for the strain and stress in silicon induced by annular Through-silicon-via (TSV) are proposed. Finite element method (FEM) is used for the model verification. It is shown that errors for the strain and stress models are respectively less than 6.6% and 6.8% for various metal and dielectric materials. Based on the analytical model of stress, keep-out-zones (KOZs) are also evaluated for pMOS and nMOS, as the stress is parallel and perpendicular to transistor channel. Annular TSVs with various materials induce KOZs of less than 6.6μm. W exhibits the best thermo-mechanical performance with KOZ=0.

A 0.8 V low-power CMOS PTAT voltage reference

A novel switching scheme for low energy charge-redistribution digital-to-analog converter (DAC) to be used in successive approximation register (SAR) analogue to-digital converters (ADCs) is presented which requires only 2 references, VREF and ground. With the monotonic capacitor switching procedure and C-2C dummy capacitor, the proposed switching scheme achieves 90.61% less switching energy, 74.7% less area and 41.18% less number of switches compared to conventional architecture, which results in an energy-efficient and switch-fewest switching scheme. Behavioral simulation results prove the effectiveness of the proposed switching scheme.