Yinxiao Yang

Breakdown current density of graphene nanoribbons

Graphene nanoribbons (GNRs) with widths down to 16 nm have been characterized for their current-carrying capacity. It is found that GNRs exhibit an impressive breakdown current density, on the order of 108 A/cm2. The breakdown current density is found to have a reciprocal relationship to GNR resistivity and the data fit points to Joule heating as the likely mechanism of breakdown. The superior current-carrying capacity of GNRs will be valuable for their application in on-chip electrical interconnects. The thermal conductivity of sub-20 nm graphene ribbons is found to be more than 1000 W/m K.

Resistivity of Graphene Nanoribbon Interconnects

Graphene nanoribbon (GNR) interconnects are fabricated, and the extracted resistivity is compared to that of Cu. It is found that the average resistivity at a given linewidth(18 nm < W< 52 nm) is about three times that of a Cu wire, whereas the best GNR has a resistivity that is comparable to that of Cu. The conductivity is found to be limited by impurity scattering as well as line-edge roughness scattering; as a result, the best reported GNR resistivity is three times the limit imposed by substrate phonon scattering. This letter reveals that even moderate-quality graphene nanowires have the potential to outperform Cu for use as on-chip interconnects.

Impact of Size Effect on Graphene Nanoribbon Transport

Graphene has shown impressive properties for nanoelectronics applications, including a high mobility and a widthdependent bandgap. Use of graphene in nanoelectronics would most likely be in the form of graphene nanoribbons (GNRs) where the ribbon width is expected to be less than 20 nm. Many theoretical projections have been made on the impact of edge scattering on carrier transport in GNRs-most studies point to a degradation of mobility (of GNRs) as well as the on/off ratio (of GNR FETs). This letter provides the first clear experimental evidence of the onset of size effect in patterned GNRs; it is shown that, for W < 60 nm, carrier mobility in GNRs is limited by edge scattering.

Binding mechanisms of molecular oxygen and moisture to graphene

We report on the binding mechanisms of oxygen and water to graphene by comparing the doping of graphene in a dry O2 environment versus in ambient. It is seen that dry oxygen dopes graphene from the basal plane while the ambient dopes graphene from the edges or from the substrate in the vicinity of the edge. Upon vacuum annealing, doping is fully reversible in the former case and only partially reversible in the latter case. We observe a thickness-dependent doping as a result of the difference in host sites for doping (basal plane versus edge). Finally, hysteresis is shown to be triggered even in dry oxygen.

p-Type Electrical Transport of Chemically Doped Epitaxial Graphene Nanoribbons

We present the first demonstration of p-type electrical transport in chemically doped epitaxial graphene (EG) nanoribbons produced on silicon carbide (SiC). The thermal annealing of cross-linked thin films of hydrogen silsesquioxane (HSQ) is found to be capable of overcoming intrinsic n-type doping from the SiC substrate, resulting in p-type functionality. A smooth transition from n- to p-type carriers, spanning a Fermi shift of 0.45 eV, is observed by controlling the density and chemical composition of HSQ. This technique provides a route for complementary transistor and interconnect fabrication, as well as facilitating chemically doped p-n junctions in EG.

System-level analysis of graphene klein tunneling device

We analyze the system-level performance of graphene-based arithmetic logic units (ALUs) enabled by Klein tunneling. Although the proposed graphene device is idealized (many experimental hurdles remain), it is important nonetheless to assess graphenes system-level prospects for logic applications to provide context for device-level research (the focus of most graphene research to date). We evaluate latency, energy, and area of graphene-enabled ALUs for (i) a 64-bit Brent-Kung adder and (ii) a 64-bit Kogge-Stone adder, both at the 32 nm technology node. The benefit in latency and energy of an ALU realized with graphene-based logic in place of silicon-based logic anticipates a hybrid graphene-silicon microprocessor.