Raghunath Murali

Breakdown current density of graphene nanoribbons

Graphene nanoribbons (GNRs) with widths down to 16 nm have been characterized for their current-carrying capacity. It is found that GNRs exhibit an impressive breakdown current density, on the order of 108 A/cm2. The breakdown current density is found to have a reciprocal relationship to GNR resistivity and the data fit points to Joule heating as the likely mechanism of breakdown. The superior current-carrying capacity of GNRs will be valuable for their application in on-chip electrical interconnects. The thermal conductivity of sub-20 nm graphene ribbons is found to be more than 1000 W/m K.

Resistivity of Graphene Nanoribbon Interconnects

Graphene nanoribbon (GNR) interconnects are fabricated, and the extracted resistivity is compared to that of Cu. It is found that the average resistivity at a given linewidth(18 nm < W< 52 nm) is about three times that of a Cu wire, whereas the best GNR has a resistivity that is comparable to that of Cu. The conductivity is found to be limited by impurity scattering as well as line-edge roughness scattering; as a result, the best reported GNR resistivity is three times the limit imposed by substrate phonon scattering. This letter reveals that even moderate-quality graphene nanowires have the potential to outperform Cu for use as on-chip interconnects.

Impact of Size Effect on Graphene Nanoribbon Transport

Graphene has shown impressive properties for nanoelectronics applications, including a high mobility and a widthdependent bandgap. Use of graphene in nanoelectronics would most likely be in the form of graphene nanoribbons (GNRs) where the ribbon width is expected to be less than 20 nm. Many theoretical projections have been made on the impact of edge scattering on carrier transport in GNRs-most studies point to a degradation of mobility (of GNRs) as well as the on/off ratio (of GNR FETs). This letter provides the first clear experimental evidence of the onset of size effect in patterned GNRs; it is shown that, for W < 60 nm, carrier mobility in GNRs is limited by edge scattering.

Single step, complementary doping of graphene

A single-step doping method capable of high resolution n- and p-type doping of large area graphene is presented. Thin films of hydrogen silsesquoxane on exfoliated graphene are used to demonstrate both electron and hole doping through control of the polymer cross-linking process. This dual-doping is attributed to the mismatch in bond strength of the Si–H and Si–O bonds in the film as well as out-gassing of hydrogen with increasing cross-linking. A high-resolution graphene p-n junction is demonstrated using this method.

Process optimization and proximity effect correction for gray scale e-beam lithography

Three-dimensional microstructures find applications in diffractive optical elements, photonic elements, etc., and can be efficiently fabricated by e-beam lithography. Good process control and efficient proximity effect correction are important for achieving the desired structures. With polymethylmethacrylate as the resist, a process optimization of different develop conditions is carried out to identify a process that is most conductive to gray scale features. A novel proximity effect correction scheme called effective dose-depth (EDD) method is proposed. Using the EDD method for grating design and the optimized process, blazed gratings have been fabricated with excellent uniformity and low surface roughness.

Pionics: the Emerging Science and Technology of Graphene-based Nanoelectronics

Extremely thin extend layers of graphene are readily grown epitaxially on single crystal silicon carbide surfaces. This material can be patterned using microelectronics lithography methods to produce all-graphene interconnected device structures. The current status of this new field of electronics is presented including the properties of several patterned devices like Hall bars and top and side gated FETs. The important role of pi electrons and their non-conventional properties of this electronic material warrants the designation of pionics for this new field of graphene-based electronics.

The Impact of Size Effects and Copper Interconnect Process Variations on the Maximum Critical Path Delay of Single and Multi-Core Microprocessors

We present a new closed-form compact model for conductor resistivity considering size effects, line-edge roughness and CMP dishing. Using this model, Monte Carlo simulations quantify the impact of interconnect variations on maximum critical path delay distributions for future technologies. Results indicate LER amplitudes start to become a substantial percentage of the nominal effective line-width dimension (2016 to 2020), leading to an increase in the conductor resistivity. Moreover, multi-core systems exhibit better tolerance to interconnect variations due to their short-wire architecture - as much as a 35% reduction for the maximum critical path delay mean degradation and standard deviation is observed for the year 2020 with a 14 nm half-pitch.

Nanoelectronics in retrospect, prospect and principle

The paramount economic development of the past half-century has been the information revolution (IR). It has given us the personnel computer, the multi-media cell phone, the Internet, and countless other electronic marvels that continuously influence our lives.. The most powerful technological driver of the IR has been the silicon microchip, for two compelling reasons [1]: First, since 1960 the productivity of microchip technology has increased by the astounding factor of one billion times! Concurrently, the performance of microchips, for example of a microprocessor chip, has increased by a factor of approximately one million times since the early 1970s. These two concurrent exponential advances sustained over decades are unmatched in technological history. Consequently, the salient objective of this discussion is to provide an incisive overview of the advance of microchips, in retrospect since 1960, in prospect from 2010 through 2024, and in principle for several following decades.

Short-channel modeling of bulk accumulation MOSFETs

Physically based short-channel effect (SCE) models are derived for bulk accumulation MOSFETs. Using the proposed models, threshold voltage rolloff, subthreshold swing, and subthreshold current can be accurately calculated; this enables physical insights into device scaling behavior, and prediction of scaling limits. The models enable optimization of accumulation MOSFETs, resulting in small SCE, and low process sensitivity. The models are equally applicable to inversion MOSFETs, and allow easy comparison between accumulation and inversion MOSFETs. Novel application areas of accumulation MOSFETs are identified where they perform better than inversion MOSFETs (better on-current and lower SCE for a given off-current). With mid-band metal gate, accumulation MOSFETs perform better than inversion MOSFETs in ultra low power applications. For poly gate CMOS, accumulation MOSFETs perform better than inversion MOSFETs in low standby power applications.

Photovoltage induced by ratchet effect in Si/SiGe heterostructures under microwave irradiation

Directed electron transport induced by polarized microwave in Si/SiGe heterostructure is investigated by patterning an array of semicircular antidots in hexagonal geometry. Carriers interact strongly with the asymmetric antidots under microwave radiation and the broken spatial symmetry drives the carriers to move preferably in one direction (ratchet effect), thereby generating a longitudinal photovoltage. In addition to this, the strong electron–electron interaction in Si/SiGe heterostructure favors a collective carrier motion along the sample edges, which gives rise to the transverse photovoltage. Both longitudinal and transverse photovoltage induced by ratchet effect opens up promising possibilities for Si/SiGe based photogalvanic detectors.