Yiorgos I. Bontzios

An evolutionary method for efficient computation of mutual capacitance for VLSI circuits based on the method of images

Abstract The problem of computing the capacitance coupling in Very Large Scale Integrated (VLSI) circuits is studied in this work. The proposed method is an approximate extended version of the method of images. The initial problem is formulated here as an optimization problem for the solution of which a genetic algorithm (GA) is employed. The proposed method is fast, general, does not rely on fitting techniques and is applicable to an arbitrary 2D or 3D geometry configuration of conductors. Extensive simulation results are presented for several practical case studies. Comparative results are given with other methods from literature and a commercial tool employing the Finite Element Method (FEM). The results show that the capacitance value computed by our method is in close agreement to the value obtained by the other methods from literature and also by the commercial tool with the average difference ranging between 2% and 5% while demonstrating better scalability as the problem complexity rises.

Prospects of 3D inductors on through silicon vias processes for 3D ICs

Three dimensional (3D) integration attempts to keep Moores Law effectively in the years to come. Through-silicon-vias (TSV) processes offer a step towards 3D integration. In this work, the aspects of inductors in the TSV technologies are studied. Various TSV inductor topologies are examined both theoretically and by means of numerical simulations. As results show, true 3D vertical inductor designs offer improvements in inductance and quality factor over the planar ones.

A Unified Method for Calculating Capacitive and Resistive Coupling Exploiting Geometry Constraints on Lightly and Heavily Doped CMOS Processes

A method for calculating capacitive and resistive coupling is developed in this work, and its implementation in commonly encountered practical cases is presented. The method is based on the geometry of the coupling mechanism, and the derived model is therefore, in general, scalable and technology independent. The constraints of any related problem can easily be incorporated into this method, whereas pure 3-D effects, such as capacitive coupling, are fast and accurately computed. The proposed method is validated using measurements from a test chip in the UMC 0.18- μm CMOS lightly doped process, simulation data obtained by two commercial simulators, and theoretical results. The accuracy of the method is shown to be within 2%-10%.

Closed-form expressions for the coupling capacitance of metal fill tiles in VLSI circuits

A new closed-form formula for the computation of the coupling capacitance of metal tiles is presented in this work. It exploits the analytical solution of the Laplace equations of equivalent studied problems. Comparative results are given with two commercial tools employing the boundary element method (BEM) and the finite element method (FEM). The results show that the capacitance value computed by the proposed formula is in close agreement to the value obtained by the simulators.

A memetic algorithm for computing 3D capacitance in multiconductor VLSI circuits

A memetic algorithm for computing the capacitance coupling in Very Large Scale Integrated (VLSI) circuits is presented in this work. The method is based on an approximate extended version of the method of images, is general and applicable to an arbitrary geometry and configuration of conductors. Simulation results are presented for several practical case studies where our method is compared with a commercial tool employing the Finite Element Method (FEM). The capacitance value computed by the proposed method is shown to be in close agreement with the value obtained by the commercial tool with the average difference kept below 3%, thus revealing the efficiency of the proposed scheme.

A Nondestructive Method for Accurately Extracting Substrate Parameters of Arbitrary Doping Profile in Nanoscale VLSI

In this paper, a new approach is presented for determining the substrate parameters of an arbitrary doping profile. It is general, technology independent, nonintrusive, and relies on simple direct-current measurements. A single measurement is required for uniform substrates, whereas two more measurements are needed for each additional layer in the multilayer case. Two different kernels are introduced for substrate resistance computation. One features a closed-form analytical solution of the Laplace equations defining the problem under study. The other relies on a geometric formulation of the current streamlines in order to compute the substrate resistance. Both simulations and measurements are exploited in order to show the validity of the proposed scheme. For measurements, data from literature are utilized and also data from a fabricated test chip. The results demonstrate that the proposed method succeeds in computing the substrate parameters fast and with high accuracy. In uniform substrates, the error falls to zero, whereas, in epitaxial substrates, the average error is kept bellow 4%.

Efficient inductance calculation for long and medium length rectangular interconnects in VLSI circuits

A method for computing mutual inductance between interconnects of rectangular geometry in Very Large Scale Integrated (VLSI) circuits is presented in this work. The method is general and does not rely on any fitting techniques. It is shown to be computational efficient and numerical stable even for very long interconnects. Simulation results with other methods from literature are presented. The mutual inductance value computed by the proposed method is shown to be in close agreement to the value obtained by the industry standard tool-FastHenry with the average error falling below 5%.

Exact closed-form expressions for substrate resistance and capacitance extraction in nanoscale VLSI

In this work a new exact formula for determining the substrate resistance and capacitance is presented. For the formula analytical results of the Laplace equations of equivalent problems are exploited. Both simulation and measurement data are utilized in order to show the validity of the proposed formula. The measurement data are obtained from a fabricated test chip. The results show that the proposed method succeeds in computing the substrate resistance.