Alkis A. Hatzopoulos

A Unified Procedure for Fault Detection of Analog and Mixed-Mode Circuits Using Magnitude and Phase Components of the Power Supply Current Spectrum

A method using the power supply current for fault detection in analog and mixed-mode circuits is presented. A new unified fault detection procedure is introduced, and its fault detection capability is estimated. The procedure combines the rms value and the magnitude and phase components of the power supply current. Certain required discrimination factors are defined, and their values are adjusted to include circuit parameter deviations and matching dependencies for the efficient application of the method. Representative results from the simulation of an operational amplifier (opamp) and a flash analog-to-digital converter circuit are given, showing the effectiveness of the proposed method.

Wavelet Analysis for the Detection of Parametric and Catastrophic Faults in Mixed-Signal Circuits

Methods for testing both parametric and catastrophic faults in analog and mixed-signal circuits are presented. They are based on the wavelet transform (WT) of the measured signal, be it supply current (IPS) or output voltage (VOUT) waveform. The tolerance limit, which affects fault detectability, for the good or reference circuit is set by statistical processing data obtained from a set of fault-free circuits. In the wavelet analysis, two test metrics, one based on a discrimination factor using normalized Euclidean distances and the other utilizing Mahalanobis distances, are introduced. Both metrics rely on wavelet energy computation. Simulation results from the application of the proposed test methods in testing known analog and mixed-signal circuit benchmarks are given. In addition, experimental results from testing actual circuits and from production line testing of a commercial electronic circuit are presented. These results show the effectiveness of the proposed test methods employing the two test metrics against three other test methods, namely, a test method based on the root-mean-square value of the measured signal, a test method utilizing the harmonic magnitude components of the measured signal spectrum, and a method based on the WT of the measured signal.

An Improved Optical Feedback Pixel Driver Circuit

An improved optical feedback circuit is proposed with only a few components and a wide range of V data voltages. Its operation is verified by simulation using the HSPICE simulator, PSIA2 thin-film transistor (TFT) model, and our previously published light-impact model of polycrystalline TFTs. In addition, the new optical feedback pixel driver (OFPD) is compared with previously published OFPDs, and its advantages are pointed out and discussed.

A complete scheme of built-in self-tests (BIST) structure for fault diagnosis in analog circuits and systems

The implementation of BIST in analog circuits is investigated, and a complete BIST scheme is proposed. This scheme can be included in any analog or mixed analog-digital circuit and can check its responses by following selected testing procedures. A CMOS chip supporting the proposed BIST structure is designed to facilitate the application of the scheme in a variety of analog circuits. Results from the application of the BIST scheme on active circuits are given, showing its effectiveness and its convenience. >

Correlation-based comparison of analog signatures for identification and fault diagnosis

Automatic fault diagnosis and circuit identification using analog signatures are considered, focusing on the automatic comparison of nearly similar analog signatures. Two known correlation-based similarity criteria are compared, and a new criterion using a weighting factor, which improves the discrimination capability, is introduced. Comparative results for various signatures are given, and useful applications of this work are discussed. >

An evolutionary method for efficient computation of mutual capacitance for VLSI circuits based on the method of images

Abstract The problem of computing the capacitance coupling in Very Large Scale Integrated (VLSI) circuits is studied in this work. The proposed method is an approximate extended version of the method of images. The initial problem is formulated here as an optimization problem for the solution of which a genetic algorithm (GA) is employed. The proposed method is fast, general, does not rely on fitting techniques and is applicable to an arbitrary 2D or 3D geometry configuration of conductors. Extensive simulation results are presented for several practical case studies. Comparative results are given with other methods from literature and a commercial tool employing the Finite Element Method (FEM). The results show that the capacitance value computed by our method is in close agreement to the value obtained by the other methods from literature and also by the commercial tool with the average difference ranging between 2% and 5% while demonstrating better scalability as the problem complexity rises.

Prospects of 3D inductors on through silicon vias processes for 3D ICs

Three dimensional (3D) integration attempts to keep Moores Law effectively in the years to come. Through-silicon-vias (TSV) processes offer a step towards 3D integration. In this work, the aspects of inductors in the TSV technologies are studied. Various TSV inductor topologies are examined both theoretically and by means of numerical simulations. As results show, true 3D vertical inductor designs offer improvements in inductance and quality factor over the planar ones.

Design and development of a versatile testing system for analog and mixed-signal circuits

In this paper the design and development of a test system based on a microcontroller is presented. This system is versatile to test various analog and mixed-signal systems without any hardware modification. Preliminary results from the application of the system to the production line testing of emergency light products are presented showing the effectiveness of the proposed testing scheme.

A Unified Method for Calculating Capacitive and Resistive Coupling Exploiting Geometry Constraints on Lightly and Heavily Doped CMOS Processes

A method for calculating capacitive and resistive coupling is developed in this work, and its implementation in commonly encountered practical cases is presented. The method is based on the geometry of the coupling mechanism, and the derived model is therefore, in general, scalable and technology independent. The constraints of any related problem can easily be incorporated into this method, whereas pure 3-D effects, such as capacitive coupling, are fast and accurately computed. The proposed method is validated using measurements from a test chip in the UMC 0.18- μm CMOS lightly doped process, simulation data obtained by two commercial simulators, and theoretical results. The accuracy of the method is shown to be within 2%-10%.

A simple built-in current sensor for current monitoring in mixed-signal circuits

Quiescent current monitoring is an interesting and efficient technique for mixed-signal testing where fault detection of analog parts requires the precise measure of the I/sub ddq/. This paper presents a very simple current sensor for on-chip current monitoring giving a precise analog output proportional to the quiescent current. Simulations show feasibility of the sensor to operate at high frequencies. This circuit may also operate at low supply voltage (/spl plusmn/1.5 V), and due to its simplicity, the silicon area overhead is very small.