Yiu-Fai Chan

A portable digital DLL for high-speed CMOS interface circuits

A digital delay-locked loop (DLL) that achieves infinite phase range and 40-ps worst case phase resolution at 400 MHz was developed in a 3.3-V, 0.4-/spl mu/m standard CMOS process. The DLL uses dual delay lines with an end-of-cycle detector, phase blenders, and duty cycle correcting multiplexers. This more easily process portable DLL achieves jitter performance comparable to a more complex analog DLL when placed into identical high-speed interface circuits fabricated on the same test-chip die. At 400 MHz, the digital DLL provides <250 ps peak-to-peak long-term jitter at 3.3 V and operates down to 1.7 V, where it dissipates 60 mW. The DLL occupies 0.96 mm/sup 2/.

A 660 MB/s interface megacell portable circuit in 0.3 /spl mu/m-0.7 /spl mu/m CMOS ASIC

A high-speed interface circuit delivering 660 MB/s data is implemented as a byte-wide I/O bus-interface cell. The interface contains low-swing input receivers, controlled-current output drivers, and clock-recovery circuits. The circuits perform well in noisy environments such as microprocessors, and withstand LdI/dt noise generated in high-inductance packages such as PQFPs. The interface is implemented as a full-custom ASIC library mega-cell, reducing area and power over gate-array approaches. An advanced CAD methodology is used to easily port the analog circuits and high-speed digital circuits in the interface cell to multiple-fabrication process technologies. The cell is used as an interface for ASIC-to-DRAM communication and for ASIC-to-ASIC communication, for point-to-point links and for bused links.

A 2.6-GByte/s multipurpose chip-to-chip interface

A 2.6 GByte/s megacell that interfaces to single or double byte wide DRAMs or logic chips is implemented using 0.35-0.18 /spl mu/m CMOS technologies. Special I/O circuits are used to guarantee 800 Mbit/s/pin data rate. Microwave PC board design methodologies are used to achieve the maximum possible interconnect bandwidth.

A portable digital DLL architecture for CMOS interface circuits

A digital DLL was developed which achieves infinite phase range and 40 ps worst-case phase resolution at 400 MHz. The architecture uses dual delay lines with an end-of-cycle detector, phase blenders, and duty cycle correctors. This more easily process-portable DLL achieves jitter performance comparable to a more complex analog DLL, when placed into identical high-speed interface circuits fabricated on the same die in a 0.4 /spl mu/m CMOS process.

A 2.6 GB/s multi-purpose chip-to-chip interface

A high-speed interface cell delivers 800 Mb/s/pin data transfer rate on a 26b wide I/O interface consisting of a dual-byte data field and a byte-wide command field. For 2.6 GB/s data rate, a 400 MHz clock recovery circuit guarantees the timing margin for transferring 800 mV swing data at both clock edges over the I/O interface. Data from the high speed interface is internally deserialized to provide a 100 MHz (f/4) ASIC clock interface. A test chip contains three megacells and built-in clock synchronization circuits to ensure proper data transfer between the three megacells with minimal impact on latency. Controlled impedance buses, referred to as channels, with careful PCB layout ensure 800 Mb/s/pin data rate on-board for ASIC-to-ASIC or ASIC-to-DRAM system configuration.