Pak Shing Chau

A portable digital DLL for high-speed CMOS interface circuits

A digital delay-locked loop (DLL) that achieves infinite phase range and 40-ps worst case phase resolution at 400 MHz was developed in a 3.3-V, 0.4-/spl mu/m standard CMOS process. The DLL uses dual delay lines with an end-of-cycle detector, phase blenders, and duty cycle correcting multiplexers. This more easily process portable DLL achieves jitter performance comparable to a more complex analog DLL when placed into identical high-speed interface circuits fabricated on the same test-chip die. At 400 MHz, the digital DLL provides <250 ps peak-to-peak long-term jitter at 3.3 V and operates down to 1.7 V, where it dissipates 60 mW. The DLL occupies 0.96 mm/sup 2/.

A 660 MB/s interface megacell portable circuit in 0.3 /spl mu/m-0.7 /spl mu/m CMOS ASIC

A high-speed interface circuit delivering 660 MB/s data is implemented as a byte-wide I/O bus-interface cell. The interface contains low-swing input receivers, controlled-current output drivers, and clock-recovery circuits. The circuits perform well in noisy environments such as microprocessors, and withstand LdI/dt noise generated in high-inductance packages such as PQFPs. The interface is implemented as a full-custom ASIC library mega-cell, reducing area and power over gate-array approaches. An advanced CAD methodology is used to easily port the analog circuits and high-speed digital circuits in the interface cell to multiple-fabrication process technologies. The cell is used as an interface for ASIC-to-DRAM communication and for ASIC-to-ASIC communication, for point-to-point links and for bused links.

1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus

A 1.6 Gb/s/pin 4-PAM multi-drop signaling system has been implemented in 0.35-/spl mu/m CMOS. The system uses current-mode single-ended signaling, with three DC references shared across six I/O pins. A high-gain windowed integrating receiver with wide common-mode range was designed in order to improve SNR when operating with the smaller input overdrive of 4-PAM. Voltage and timing margins are measured via shmoos in a two-drop bussed system.

A multiple vendor 2.5-V DLL for 1.6-GB/s RDRAMs

A DLL design and porting methodology have been described to enable multiple vendors to create a 400 MHz DLL from a template design in a 0.25 /spl mu/m, 64 Mb DRAM process.

A portable digital DLL architecture for CMOS interface circuits

A digital DLL was developed which achieves infinite phase range and 40 ps worst-case phase resolution at 400 MHz. The architecture uses dual delay lines with an end-of-cycle detector, phase blenders, and duty cycle correctors. This more easily process-portable DLL achieves jitter performance comparable to a more complex analog DLL, when placed into identical high-speed interface circuits fabricated on the same die in a 0.4 /spl mu/m CMOS process.

A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface

A 800 Mb/s to 3.2 Gb/s memory interface is designed that achieves 30% improved energy efficiency by eliminating idle mode power completely. The link is similar to a standard DDR architecture with the addition of a fast-lock DLL on the memory side that wakes up from 0 mW and locks within 3 clock cycles consuming 24 mW with residual timing error less than 33 mUI. Following initial lock, the DLL operates in a closed loop to compensate for V,T drift consuming 6 mW @ 1.6 GHz including a replica buffer. By incorporating an injection locked oscillator inside the loop, the DLL provides PLL like high frequency input jitter filtering, and corrects ±10% DCD without an additional duty cycle correction loop.

An integrated VCSEL driver for 10Gb ethernet in 0.13/spl mu/m CMOS

A 10.3Gb/s VCSEL driver is integrated with a complete Ethernet transceiver in a standard 0.13mum CMOS process. When driving a VCSEL differentially, the resulting optical eye exceeds the 10Gb/s Ethernet mask by 35%. Intended for short-reach applications, the driver dissipates 85mW from 1.2V and occupies 0.15mm2