Yiwen Xu

Light extraction efficiency of a top-emission organic light-emitting diode with an Yb/Au double-layer cathode and an opaque Si anode

We have computed the transmittances of four types of cathode--Yb/Au, Al/Au, Yb/Ag, and Al/Ag double layers--and the light extraction efficiencies of the top-emission organic light-emitting diodes with these cathodes, respectively, based on the characteristic matrix method and the dissipation spectrum model. Computations show that the Yb/Au cathode has a markedly higher transmittance than the other three types of cathode when the Yb and Au thicknesses in the Yb/Au cathode are, respectively, equal to the Al (or Yb) and Au (or Ag) thicknesses in the other three types of cathode. The power lost to the Yb/Au cathode due to the surface plasmon polaritons is the lowest, and hence the device with the Yb/Au cathode has the highest extraction efficiency. The transmittances for the four cathodes are also measured experimentally.

Organic light-emitting diodes with n-type silicon anode

In an AIQ-based bilayer organic light-emitting diode, n-type silicon has been used as an anode, and semitransparent metals Sm (15 nm)/Au (15 nm) as a cathode. This device has much smaller currents at high voltages (> 8 V) and a higher turn-on voltage than the device with an identical structure but an indium-tin oxide anode. By successively depositing ultra thin films of Au and AIQ on the n-Si surface, the device performances are improved significantly, reaching a power efficiency of 0.1 Im W-1 and a current efficiency of 0.7 cd A(-1) at 15.9 V and 0.3 mA mm(-2). The mechanisms for the hole injection and performance improvement are discussed.

A carrier-based analytic drain current model incorporating velocity saturation for undoped surrounding-gate MOSFETs

A carrier-based analytic drain current model including the velocity saturation effect for the undoped surrounding-gate (SRG) MOSFETs is developed in this paper. Based on the previously ideal carrier-based drain current model, the Caughey–Thomas mobility model with an exponent factor n = 2 is applied and integrated into the analytic drain current model development. The validity of the presented model is confirmed by comparisons with three-dimensional (3D) TCAD device simulations for good agreements between the model prediction and numerical simulation on transfer/output characteristics and trans/output-conductance of the SRG MOSFETs are obtained in the whole operation regions from subthreshold to strong inversion and from linear to saturation regions. The symmetry property of the developed drain current model is guaranteed by the exponent factor n = 2 in the Caughey–Thomas model and also further tested, promoting the analog circuit design function of the proposed model.

Numerical simulation on novel nano-scale lateral double-gate tunneling field effect transistor

A novel nano-scale lateral double-gate tunneling field effect transistor (LDG-TFET) is proposed in this paper and its performance is shown through two dimensional device numerical simulations. The study result demonstrates that this new tunneling transistor allows for the steeper sub-threshold swings, e.g. below 60 mV/Dec, the super low supply voltage, e.g. operable at VDD ≪0.2V and the high ratio between the turn-on and turn-off current for the availability of high-k/metal stack materials. This tunneling field effect transistor may be integrated with present CMOS process and architecture with some specific applications such as memories because of the low turn-off current and when the delay is truly determined by interconnects because of its high turn-on/turn off ratio, which are important for next generation of micro-power and ultra-low integrated circuits.

Hole-injection mechanisms of organic light emitting diodes with Si anodes

We have studied the hole-injection mechanisms of two types of Si anodes, polycrystalline Si (poly-Si) film and crystal Si (c-Si) wafer anodes, in organic light emitting diodes (OLEDs) and those of OLEDs with indium tin oxide anodes. It was found that the hole-injection mechanisms of these devices are very different from each other. The hole injection of the c-Si anode obeys the classic Richardson thermionic emission model and that of the poly-Si film anode agrees well with the modified thermionic emission model (Scott and Malliaras 1999 Chem. Phys. Lett. 299 115-9). When the c-Si anode is covered with a thin SiO2 layer, its hole injection changes to obey the modified thermionic emission model.

Simulation study on a new dual-material nanowire MOS surrounding-gate transistor

In this paper, a novel field effect nanowire MOS transistor taking advantage of both dual-material gate and surrounding gate is proposed and performance characteristics are demonstrated numerically in detail. Surrounding-gate transistor is known to be used to enhance the electrostatic control of the channel, and dual-material-gate structure is extended from split-gate field effect transistor to obtain larger current and better short-channel performance. Three dimensional device simulations with Sentaurus Device are performed on this dual-material surrounding-gate transistor. Higher driving current, high I ON /I OFF ratio and suppressed short-channel effects are obtained with this novel device structure.

Study on electron mobility in nanoscale DG MOSFETs with symmetric, asymmetric and independent operation modes

Electron mobility in nanoscale double-gate (DG) MOSFETs with symmetric, asymmetric and independent operation modes is studied in this paper by using a comprehensive numerical model. A numerical program is first developed and then the dependence of electron mobility on device geometry and bias conditions are simulated. It is shown that that electron mobility changes monotonically with effective field in symmetric conditions while a peek in the curve of phonon-limited mobility versus the gate biases shows a new feature due to the impact of effective field on intra-valley and inter-valley scattering for independent gate operation mode.

Numerical simulation study on electron mobility of independent DG MOSFETs

Numerical simulation study on electron mobility in independent DG MOSFETs with back gate biased in accumulation, flatband and inversion operation regions is presented in this paper. A numerical simulation program of the electron transport in the independent DG MOSFETs, which includes both phonon and surface roughness scattering mechanisms, is developed. From it, the dependence characteristics of the DG MOSFET electron mobility on the device operation conditions and the structure parameters are discussed. It is shown that DG MOSFET exhibits higher mobility when back gate is biased in inversion region compared to simulation results when back gate is in flat-band or accumulation regions. Mobility enhancement is observed in devices with thinner silicon film, when higher field is applied, which can be attributed to “volume inversion” in DG MOSFET.