Frank He

A Novel Barrier Controlled Tunnel FET

A novel structure of tunnel field-effect transistor (FET) is introduced with the gate composed of three segments of different work functions. The tunnel current is controlled by an in channel potential barrier as well as the source-channel tunnel junction bandgap, which combines the merits of both bandgap-controlled tunnel FET and barrier-controlled traditional MOSFET. Intuitive explanation is provided for this novel device structure. The performance enhancement is confirmed by numerical simulation with carbon nanotube as the channel material. This structure is especially suitable for bandgap tunable ballistic transport materials (e.g., carbon nanotube and graphene nanoribbon).

The impact of device parameter variation on double gate tunneling FET and double gate MOSFET

Impacts of parameter variations on the performance of double-gate (DG) tunneling FET (TFET) and conventional DG MOSFET are investigated by TCAD simulations. The different operation mechanisms determined their sensitivities to parameter variations. Variations in channel doping concentrations, gate oxide thickness, silicon film thickness and offset of gate electrode are studied in this work. It is found that though TFET overcomes the minimum subthreshold swing (SS) limit in conventional MOSFET, it is more sensitive to parameter variation, especially to gate oxide and silicon film thickness.

FinFET: From compact modeling to circuit performance

FinFET device, the promise one of all candidates which may extend CMOS scaling to 10nm and beyond, has attracted intensive research interest in recent years. In paralleling the process technology and circuit design methodology, a compact model which serves as a link between the process technology and circuit design is strongly demanded. In this paper, we first review the FinFET process technology including SOI-FinFET and bulk-FinFET. Then a potential-based compact model is proposed to describe the electrical characteristics of the FinFET transistor. The model is verified by 2-D numerical simulation and is implemented into HSPICE simulator. Finally, the reliability issue of the FinFET device and circuit functions are illustrated and analyzed, which are important for the practical applications and circuit design.

Generic DG MOSFET analytic model with vertical electric field induced mobility degradation effects

A generic DG MOSFET analytic model with vertical electric field induced mobility degradation effects is proposed and verified in this paper. It is shown that the proposed model is valid for different operation modes including symmetric DG (sDG), asymmetric DG (aDG) and independent DG (iDG). Extensive two-dimensional (2-D) device simulation is performed to verify the proposed model.

A Web-Based Platform for Nanoscale Non-classical Device Modeling and Circuit Performance Simulation

This paper describes a web-based platform for nanoscale non-classical device modeling and circuit simulation, especially for non-classical CMOS device compact modeling and circuit performance prediction. This platform is based on program libraries, including model code files. We use SPICE as circuit simulation framework, and the Verilog-A as model design language. Based on the user input deck content, running embedding device and circuit programs, the platform produces several types of device characteristics output such as data texts and graphs on the web page for analysis, according to the simulation results and users’ requests. Some nanoscale device modeling examples and the circuit simulation cases are demonstrated by the means of the platform configures and function application. It is shown that not only does this kind of platform address problems arising from the dependence on computer operating system of modeling and simulation software, the complexity of software and program update, but also helps researchers focus on their research on device physics and circuit design, display their research results and share latest research achievements or new technology online, which will accelerate the development of device modeling and circuit design technology in turn.

Numerical simulation of programming and read process for nano-scale phase-change memory (PCM) cell

As one of the candidates of the next generation non-volatile memory(NVM), phase change memory(PCM) has been paid more attention. However, there are still many open issues such as numerical simulation to study. Phase transition is a temperature based process, which can be simulated by temperature profile generated by the device simulator coupled with the phase transition model. In this work, a phase transition model is implemented, which can provide the amorphization process simulation and the nucleation process simulation, and the set and reset process are simulated. Meanwhile the readout I-V characteristics are simulated and discussed.

Asymmetric issues of FinFET device after hot carrier injection and impact on digital and analog circuits

This paper presents the asymmetric issue of FinFET device after hot carrier injection (HCI) effect and impact on the digital and analog circuits. The interface state distribution along the FinFET channel is first extracted from hot carrier injection experimental data, and then develops a compact FinFET model to simulate the impact on asymmetric distribution of interface states to the device characteristics. The results show that the asymmetric degradation is much more significant in Ids-Vds characteristics than in Ids-Vgs characteristics. On the other hand, digital and analogy circuits exhibit different asymmetric performance degradation in various operation cases.

A novel approach to simulate Fin-width Line Edge Roughness effect of FinFET performance

This paper developed a full three-dimensional (3-D) statistical simulation approach to investigate Fin-width Line Edge Roughness (LER) effect on the FinFETs performance. The line edge roughness is introduced by Matlab program, and then the intrinsic parameter fluctuations at fixed LER parameters are studied in carefully designed simulation experiments. The result shows that Fin-width LER causes a dramatic shift and fluctuations in threshold voltage. The simulation results also imply that the velocity saturation effect may come into effect even under low drain voltage due to LER effect.

Numerical simulation on novel nano-scale lateral double-gate tunneling field effect transistor

A novel nano-scale lateral double-gate tunneling field effect transistor (LDG-TFET) is proposed in this paper and its performance is shown through two dimensional device numerical simulations. The study result demonstrates that this new tunneling transistor allows for the steeper sub-threshold swings, e.g. below 60 mV/Dec, the super low supply voltage, e.g. operable at VDD ≪0.2V and the high ratio between the turn-on and turn-off current for the availability of high-k/metal stack materials. This tunneling field effect transistor may be integrated with present CMOS process and architecture with some specific applications such as memories because of the low turn-off current and when the delay is truly determined by interconnects because of its high turn-on/turn off ratio, which are important for next generation of micro-power and ultra-low integrated circuits.

Two-transistor active pixel image sensor with active diode reset

A two-transistor active pixel image sensor (2T-APS) architecture is proposed. Instead of a reset transistor, a diode within the pinned photodiode sensor is used to reset the charge-sensing node in each pixel without any extra area. The new architecture can be used to increase the fill factor and/or reduce the pixel pitch. A test structure of the 2T-APS has been demonstrated using 0.35 µm CMOS technology featuring a 7µm × 7µm pixel size with a fill factor of 38%. The pixel characteristics are presented and discussed.