Steven B. Bibyk

Design of a wireless sensor network platform for detecting rare, random, and ephemeral events

We present the design of the extreme scale mote, a new sensor network platform for reliably detecting and classifying, and quickly reporting, rare, random, and ephemeral events in a large-scale, long-lived, and ret askable manner. This new mote was designed for the ExScal project which seeks to demonstrate a 10,000 node network capable of discriminating civilians, soldiers and vehicles, spread out over a 10 km/sup 2/ area, with node lifetimes approaching 1,000 hours of continuous operation on two AA alkaline batteries. This application posed unique functional, usability, scalability, and robustness requirements which could not be met with existing hardware, and therefore motivated the design of a new platform. The detection and classification requirements are met using infrared, magnetic, and acoustic sensors. The infrared and acoustic sensors are designed for low-power continuous operation and include asynchronous processor wakeup circuitry. The usability and scalability requirements are met by minimizing the frequency and cost of human-in-the-loop operations during node deployment, activation, and verification through improvements in the user interface, packaging, and configurability of the platform. Recoverable retasking is addressed by using a grenade timer that periodically forces a system reset. The key contributions of this work are a specific design point and general design methods for building sensor network platforms to detect exceptional events.

Towards radar-enabled sensor networks

Ultra wideband radar-enabled wireless sensor networks have the potential to address key detection and classification requirements common to many surveillance and tracking applications. However, traditional radar signal processing techniques are mismatched with the limited computational and storage resources available on typical sensor nodes. The mismatch is exacerbated in noisy, cluttered environments or when the signals have corrupted spectra. To explore the compatibility of ultra wideband radar and mote-class sensor nodes, we designed and built a new platform called the radar mote. An early prototype of this platform was used to detect, classify, and track people and vehicles moving through an outdoor sensor network deployment. This paper describes the sensors theory of operation, discusses the design and implementation of the radar mote, and presents sample signal waveforms of people, vehicles, noise, and clutter. We demonstrate that radar sensors can be successfully integrated with mote-class devices and imbue them with an extraordinarily useful sensing modality

Frequency-Selective Predistortion Linearization of RF Power Amplifiers

This paper presents a frequency-selective RF vector predistortion linearization system for RF multicarrier power amplifiers (PAs) affected by strong differential memory effects. Differential memory effects can be revealed in two-tone experiment by the divergence for increasing tone-spacing of the vector Volterra coefficients associated with the lower and upper intermodulations tones. Using large-signal vector measurement with a large-signal network analyzer, a class-AB LDMOS RF PA is demonstrated to exhibit a strong differential memory effect for modulation bandwidth above 0.3 MHz. New frequency-selective RF and baseband predistortion linearization algorithms are proposed to separately address the linearization requirements of the interband and inband intermodulation products of both the lower and upper sidebands. Theoretical verification of the algorithms are demonstrated with Matlab simulations using a Volterra/Wiener PA model with memory effects. The baseband linearization algorithm is next implemented in a field-programmable gate array and experimentally investigated for the linearization of the class-AB LDMOS PA for two carrier wideband code-division multiple-access signals. The ability of the algorithm to selectively linearize the two interband and four inband intermodulation products is demonstrated. Adjacent channel leakage ratio of up to 45 dBc for inband and interband are demonstrated experimentally at twice the typical fractional bandwidth.

A very low frequency, micropower, low voltage CMOS oscillator for noncardiac pacemakers

One of the most power consuming components of a modern noncardiac pacemaker is the oscillator circuitry. This brief details the design of a micropower, low voltage, low frequency oscillator consisting of CMOS devices operating in subthreshold. Since the frequency of a typical oscillator is proportional to Current/Capacitance, the operation of the transistors in the subthreshold region allows the size of the capacitance to be reduced significantly in addition to decreasing the quiescent power consumption. The proposed prototype oscillator was fabricated in a 2 /spl mu/m n-well CMOS process and occupies 0.281 mm/sup 2/ including a 100 pf capacitor which takes 77.8% (0.219 mm/sup 2/) of the total area. Experimental results show a frequency of oscillation as low as 0.3 Hz and a power consumption of around 0.24 /spl mu/W at 0.3 Hz to 0.3 /spl mu/W at 100 Hz with a 2 V supply voltage.

Real-time video compression using differential vector quantization

This paper describes hardware that has been built to compress video in real time using full-search vector quantization (VQ). This architecture implements a differential-vector-quantization (DVQ) algorithm and features a special-purpose digital associative memory, the VAMPIRE chip, which has been fabricated in 2 /spl mu/m CMOS. We describe the DVQ algorithm, its adaptations for sampled NTSC composite-color video, and details of its hardware implementation. We conclude by presenting both numerical results and images drawn from real-time operation of the DVQ hardware. >

Combinatorial pulse position modulation for power-efficient free-space laser communications

A new modulation technique called combinatorial pulse position modulation (CPPM) is presented as a power-efficient alternating to quaternary pulse position modulation (QPPM) for direct-detection, free-space laser communications. The special case of 16C4PPM is compared to QPPM in terms of data throughput and bit error rate (BER) performance for similar laser power and pulse duty cycle requirements. The increased throughput from CPPM enables the use of forward error corrective (FEC) encoding for a net decrease in the amount of laser power required for a given data throughput compared to uncoded QPPM. A specific, practical case of coded CPPM is shown to reduce the amount of power required to transmit and receive a given data sequence by at least 4.7 dB. Novel hardware techniques for maximum likelihood detection and symbol timing recovery are presented.

Issues in Analog VLSI and MOS Techniques for Neural Computing

Issues in analog VLSI, such as the use of simple parameterized cells that are highly reconfigurable and input/output compatability, are being molded by the activities in developing hardware implementations of microelectronic neural networks. Analog MOS circuit modules, such as integrators, summers, and multipliers can be configured in a neural network architecture to build feedback/feedforward neural networks and/or the equivalent of adaptive, state-space signal processors. The methods of adaptation can be compared by evaluating a criterion or energy function which drives the adaptation process.

A new fast-settling gearshift adaptive PLL to extend loop bandwidth enhancement in frequency synthesizers

The loop bandwidth of PLL frequency synthesizers involves design tradeoffs between the lock time and reference feedthrough. The adaptive PLL solves the problem by increasing the bandwidth in the acquiring stage for faster lock speed and reducing the bandwidth after the loop locks for lower spur level. However, the loop bandwidth in the speedup mode is constrained to approximately 1/10 of the reference frequency for stability considerations. In this paper, the theoretical bandwidth limitation is explored with a simple nonlinear sampling delay model. A new adaptation scheme is proposed that extends the loop bandwidth enhancement by adaptively controlling the reference frequency in a gear-shifting approach. In the speedup mode, the loop bandwidth is enhanced by up to 64 times due to the increased reference frequency, resulting in a fast settling time of 229 /spl mu/s to within 20 kHz for a 80 MHz frequency step in a 200 kHz channel spacing synthesizer.

CAD latches onto new techniques for analog ICs

Design techniques for low-power, nondigital nonmicrowave circuits are presented. The major objectives in improving analog CAD are described. The current status of CAD for analog circuits is discussed, and interesting trends are examined. An approach to CAD-compatible analog design is discussed. These designs also apply to mixed analog/digital VLSI design environments, particularly to circuits used in signal processing.<<ETX>>

A novel all-MOS high-speed continuous-time filter

A new continuous-time transistor-only bandpass/lowpass filter based on g/sub m//C integrators that is capable of realizing critical frequencies in excess in 10 MHz is described. The center frequency, Q, and voltage gain are all voltage-tunable over a 10:1 range. The integrators use a novel, fully balanced, source-degenerated transconductor which maintains less than 1% nonlinearity for differential inputs up to 2 V. A second-order state variable filter with a nominal f/sub 0/=3.2 MHz and Q=5 consumes only 20 mW from a single-ended 5-V supply.<<ETX>>