Adem Aktas

A single-chip CMOS transceiver for 802.11a/b/g wireless LANs

A dual-band trimode radio fully compliant with the IEEE 802.11a, b, and g standards is implemented in a 0.18-/spl mu/m CMOS process and packaged in a 48-pin QFN package. The transceiver achieves a receiver noise figure of 4.9/5.6 dB for the 2.4-GHz/5-GHz bands, respectively, and a transmit error vector magnitude (EVM) of 2.5% for both bands. The transmit output power is digitally controlled, allowing per-packet power control as required by the forthcoming 802.11 h standard. A quadrature accuracy of 0.3/spl deg/ in phase and 0.05 dB in amplitude is achieved through careful analysis and design of the I/Q generation parts of the local oscillator. The local oscillators achieve a total integrated phase noise of better than -34 dBc. Compatibility with multiple baseband chips is ensured by flexible interfaces toward the A/D and D/A converters, as well as a calibration scheme not requiring any baseband support. The chip passes /spl plusmn/2 kV human body model ESD testing on all pins, including the RF pins. The total die area is 12 mm/sup 2/. The power consumption is 207 mW in the receive mode and 247 mW in the transmit mode using a 1.8-V supply.

CMOS PLL calibration techniques

The article discusses auto calibration of phase lock loops (PLLs), particularly when used as frequency synthesizers in fully integrated radios targeting future generations of broadband wireless applications. These PLLs use wideband voltage-controlled oscillators (VCOs) covering a wide tuning range. A calibration technique is discussed and used in a wireless LAN radio.

A single chip CMOS transceiver for 802.11 a/b/g WLANs

A 0.18 /spl mu/m dual-band tri-mode CMOS radio, fully compliant with the IEEE 802.11 a/b/g standards, achieves a system noise figure of 5.2/5.6 dB (high gain), and an EVM of 2.7/3.0% for the 2.4/5 GHz bands, respectively. Die area is 12 mm/sup 2/, and power consumption is 200 mW in RX and 240 mW in TX using a 1.8 V supply.

Pad de-embedding in RF CMOS

In this article, we discuss techniques for RF pad layout and de-embedding, a topic of great interest particularly for implementing radio frequency (RF) circuits in mainstream CMOS technology.

A fully integrated dual-mode frequency synthesizer for GSM and Wideband CDMA in 0.5/spl mu/m CMOS

A fully integrated dual-mode frequency synthesizer for GSM and Wideband CDMA (WCDMA) is presented. The synthesizer is designed to maximize hardware sharing between the two modes by applying fractional frequency synthesis to GSM mode and integer frequency synthesis to WCDMA mode. The shared components include phase frequency detector (PFD), charge pump (CP), loop filter, integer frequency divider and VCO, which is 70% of the entire synthesizer in term of die area. A high-speed low power dual modulus prescaler is proposed to operate up to 2.1GHz at 3.3V supply voltage with 11.6mW power consumption by simulation. A dual mode VCO is also proposed for the enhanced tuning range with an accumulation mode NMOS varactor for band-to-band tuning and a p/sup +/n junction varactor for in-band tuning. The simulation result shows that the synthesizer phase noise is -112dBc/Hz at 600kHz offset frequency for WCDMA mode and -117 dBc/Hz for GSM mode.

A High-Speed Low-Power Divide-by-15/16 Dual Modulus Prescaler in 0.6 μm CMOS

A new high-speed low-power dual modulus prescaler (DMP) topology is proposed. In this DMP, the synchronous part is designed as a divide-by-3/4 divider using a state-selection scheme. Compared with the conventional divide-by-4/5 divider, it has a higher speed by eliminating the NAND-gate introduced critical path delay, as well as a lower power consumption by minimizing the number of full-speed D-type flip-flops (DFFs) required. Based on this topology, a divide-by-15/16 DMP is implemented in the 0.6 μm standard CMOS process. Simulation result shows that a maximum operating frequency of 2.15 GHz is obtained at 3.3 V supply with a power consumption of 11.6 mW. The circuit can operate above 3 GHz with 5 V supply and down to 1.5 V supply voltage with 570 MHz input frequency.

A single chip 802.11 a/b/g WLAN transceiver

A dual-band triple mode radio compliant with the IEEE 802.11 a/b/g standard implemented in a 0.18 μm CMOS process b presented. The transceiver is compatible with a large number of basebands due to its flexible interface towards AD / DA converters and on-chip automatic calibration of-on-chip filters and oscillators. The transceiver achieves a receiver noise figure of 4.9/5.MB for the 2.4GHz/5GHz bands, respectively, and a minimum transmit error vector magnitude (EVM) of 2.5% for both bands. A quadrature accuracy of 0.3° in phase and 0.05dB in amplitude is achieved through careful analysis and design of the I/Q generation parts of the local oscillator. The local oscillators achieve a better than -34dBc total integrated phase noise. The chip passes ± human body model ESD testing on all pins, including the RF pins. The total die area is 12mm2. The power consumption is 207mW in the receive mode and 247mW in the transmit made using a 1.8Vsupply.

Phase-Locked Loop Techniques in Modern Communications Systems

Publisher Summary In modern receivers for wireless applications, channels are selected by mixing an incoming RF signal with a local oscillator signal. One popular and affordable method of tuning is employing a frequency synthesizer based on a phase-locked loop (PLL). Because coherent systems have higher noise immunity than non-coherent systems, coherent systems are highly preferred in modern wireless communication systems. In order to eliminate the static phase error, it is desirable to make the system have additional pole at the origin. This type of system is a type-II system as there are two poles at the origin. A PLL has various frequency ranges to specify its tracking/acquisition performance lock-range, pull-in range, and hold-range. When the reference signal is leading the feedback signal, the output will produce more positive area and thus a higher level of control voltage. The phase detection range of phase detectors depends on the devices used. A PLL forces the divided frequency to be exactly equal to the frequency of the input signal in the lock mode. This chapter highlights that the most critical specification for any oscillator is its spectral purity.

A single chip radio transceiver for 802.11a/b/g WLAN in 0.18/spl mu/ CMOS

This paper presents design and performance of a single chip CMOS radio covering the Wi-Fi 802.11 a(5GHz) and 802.11 b(2.4GHz), and a draft version of the 802.11 g(2.4 GHz OFDM/CCK) wireless standard. The radio is based on a configurable and digitally programmable transceiver architecture and adopts a frequency plan that: a) avoids use of external image reject filters and b) allows design of integrated low phase noise frequency synthesizer, as required by 54Mb/s 64-QAM modulation, while maintaining low power consumption. The resulting solution achieves maximum hardware share as mixers, PLLs and analog baseband chains are shared amongst the three standards. It was implemented in 0.18/spl mu/ CMOS technology with a die size of 12 mm/sup 2/ in a 48-pin package.