Yoav Weizman

A simple system for on-die measurement of atto-Farad capacitance

Charge Injection Error Free (CIEF) Charge-Base Capacitance Measurement (CBCM) technique provides a simple way for accurate measurements of on-chip interconnect parasitic capacitance. We report here for the first time capacitance measurements of on-chip interconnect with resolution values of 1aF or better. We analyze the setup requirements to allow such capability, and show stable coupling capacitance measurement results at the 1aF resolution.

Radon-Transform-Based Image Enhancement for Microelectronic Chip Inspection

In this paper, we present a new numerical approach for enhancing the resolving power of low-resolution (LR) images, which can be applied for failure analysis of microelectronic chips. The resolution improvement is based upon a numerical iterative comparison between a Radon transform of a high-resolution layout image and a Radon transform of an LR experimentally captured image of the same region of interest.

Superresolved Imaging of Microelectronic Devices for Improved Failure Analysis

In this paper, we present a new numerical approach for improving the resolving power of low-resolution (LR) images. This approach may be applied for failure analysis of microelectronic chips. The resolution improvement is based upon numerical iterative comparison between a LR experimentally captured image and a high-resolution layout image of the same region of interest.

Investigation of on-chip PLL irregularities under stress conditions - case study

In modern high performance VLSI design, on-chip phase locked loop (PLL) performance degradation due to intensive core switching activities is becoming an influential factor. Under certain borderline conditions, the PLL may become unstable. The analysis herein describes PLL irregularities under marginal mode, frequency and voltage conditions combined with intensive core operations. After lengthy analysis that included step-by-step elimination of all noise sources, the cause of instability was explained by coupling between a voltage spike on core power supply line and the internal control signal of the voltage controlled oscillator of the PLL through the chip substrate. The solution to the problem was suggested by changing the PLL dynamic characteristics. Through this investigation we studied the noise crosstalk issue in mixed mode (analog and digital) systems and also the PLL dynamics under stress conditions, which demonstrates the complexity of PLL analysis in a system-on-chip environment.

Improving failure analysis navigation Using optical super resolved imaging

The authors present a new numerical approach for improving the resolving power of low resolution images which is applied for failure analysis of microelectronic chips. The resolution improvement is based upon a numerical iterative comparison between a high resolution layout image and a low resolution experimentally captured image of the same region of interest.