Yogesh Pratap

Performance Evaluation and Reliability Issues of Junctionless CSG MOSFET for RFIC Design

This paper investigates the reliability issues of junctionless cylindrical surrounding-gate (JL CSG) MOSFET by employing temperature variations, ranging from 200 K to 500 K, along with the influence of interface trap charges. Furthermore, the analog/RF performance evaluation and linearity distortion analysis due to the interface trap charges in terms of figure-of-merit metrics, i.e., drain current Ids; intrinsic gain (gm/gd) Ion/Ioff ; cutoff frequency fT; gain; gain transconductance frequency product; IMD3; VIP2; VIP3; IIP3; and higher order transconductance coefficients gm1, gm2, and gm3 of JL CSG MOSFET have been carried out. A direct comparative study in terms of performance degradation is made between gate material engineered (GME) and single-material gate (SMG) JL CSG MOSFET using ATLAS 3-D device simulator. Simulation results reveal that a GME JL transistor shows better immunity against the influence of interface trap charges and exhibits significant enhancement to maintain device linearization, as compared to an SMG JL CSG MOSFET, so that it can be used as a high-efficiency linear radio-frequency integrated-circuit design and wireless applications. Also from simulation study, degrading effects in JL CSG MOSFET are more pronounce at low temperature and subthreshold region. Apart from analog/RF performance, trap charges change the temperature sensitivity coefficient of the drain current and zero crossover point.

An analytical subthreshold current modeling of cylindrical gate all around (CGAA) MOSFET incorporating the influence of device design engineering

Abstract An analytical model of CGAA MOSFET incorporating material engineering, channel engineering and stack engineering has been proposed and verified using ATLAS 3D device simulator. A comparative study of short channel effects for various device structures has also been carried out incorporating the effect of drain induced barrier lowering (DIBL), threshold voltage lowering and degradation of subthreshold slope. The effectiveness of applying the three region doping profile concept in the channel such as high-medium-low and low-high-low and its comparison with Gaussian doping profile to the cylindrical GAA MOSFET has been examined in detail. Reduced SCEs have been evaluated in combined designs i.e. TM–GC–GS, GCGS and DM–GC–GS. Out of several design engineering, GC–GS CGAA gives nearly ideal subthreshold slope whereas TM–GC–GS CGAA provides overall superior performance to reduce SCEs in deep nano-meter. The results so obtained are in good agreement with the simulated data which validate the model.

Localized Charge-Dependent Threshold Voltage Analysis of Gate-Material-Engineered Junctionless Nanowire Transistor

In this paper, the threshold voltage analysis of junctionless nanowire transistor (JNT) due to radiation/ process/stress/hot-carrier damage-induced localized/fixed charges at elevated temperatures is discussed. A temperature-dependent threshold voltage model for JNT with localized charges has been developed including the source/drain depleted regions. The impact of position, density, and polarity of localized charges on channel potential, bandgap energy, and threshold voltage is studied. Four different localized charge density profiles have been used to evaluate the performance degradation. The results demonstrate that localized charges significantly change the device threshold voltage and temperature sensitivity and show less detrimental effect at elevated temperatures.

Cylindrical gate all around Schottky barrier MOSFET with insulated shallow extensions at source/drain for removal of ambipolarity: a novel approach

In this paper TCAD-based simulation of a novel insulated shallow extension (ISE) cylindrical gate all around (CGAA) Schottky barrier (SB) MOSFET has been reported, to eliminate the suicidal ambipolar behavior (bias-dependent OFF state leakage current) of conventional SB-CGAA MOSFET by blocking the metal-induced gap states as well as unwanted charge sharing between source/channel and drain/channel regions. This novel structure offers low barrier height at the source and offers high ON-state current. The I ON / I OFF of ISE-CGAA-SB-MOSFET increases by 1177 times and offers steeper subthreshold slope (~60 mV/decade). However a little reduction in peak cut off frequency is observed and to further improve the cut-off frequency dual metal gate architecture has been employed and a comparative assessment of single metal gate, dual metal gate, single metal gate with ISE, and dual metal gate with ISE has been presented. The improved performance of Schottky barrier CGAA MOSFET by the incorporation of ISE makes it an attractive candidate for CMOS digital circuit design. The numerical simulation is performed using the ATLAS-3D device simulator.

DMG insulated shallow extension cylindrical GAA Schottky Barrier MOSFET for removal of ambipolarity: A novel approach

This paper proposes a novel Dual Metal Gate (DMG) Insulated Shallow Extension (ISE) Cylindrical Gate All Around (CGAA) Schottky Barrier (SB) MOSFET to eliminate the ambipolar behaviour of SB-CGAA MOSFET by blocking the metal induced gap states as well as unwanted charge sharing between source/channel and drain/channel regions. The Ion/Ioff ratio of DMG-ISE-CGAA-SB MOSFET increases by 362 times offering steeper subthreshold slope (67.59 mV/decade) and improved cut-off frequency makes it attractive candidate for CMOS digital circuit design.

Sensitivity investigation of gate-all-around junctionless transistor for hydrogen gas detection

In recent time, a MOSFET based gas sensor has been widely used for low cost and high sensitive sensor for a wide range of industrial and domestic applications. In this paper, a gate-all-around Gas-sensing Junctionless Nanowire Transistor (G-JNT) with catalytic metal gate i.e. palladium (Pd) is proposed for the first time for high sensitivity and low power hydrogen gas detection using ATLAS-3D device simulator. Shift in channel potential, subthreshold current and in threshold voltage is used to predict the response of the sensor. Impact of silicon pillar radius, gate oxide width and gate length on the sensitivity of G-JNT has been investigated in details. Results exhibit that junctionless Transistor with catalytic metal gate is the suitable candidate for hydrogen molecule detection.

Impact of asymmetric gate stack on a junctionless CSG MOSFET for enhanced hot carrier reliability

This paper reports the impact of asymmetric gate stack architecture (AGSA) on a junctionless cylindrical surrounding gate (JL-CSG) MOSFET to improve the hot carrier reliability and electrostatic control. The novel structure is based upon asymmetric gate stack architecture by combining high-k gate dielectric at source side and vacuum gate dielectric at drain side which significantly reduces electric field, electron temperature and drain induced gate leakage. A comparative performance evaluation of short channel effects (SCEs) between a new device structure, AGSA JL-CSG MOSFET, and a conventional JL-CSG MOSFET has been carried out. The figure of merit (FOM) metrics such as electric field, surface potential, electron temperature, drain current (Ids) and transconductance (gm) have been investigated. The vacuum dielectric enhances immunity against hot carrier induced damage and high-k dielectric improves the analog/RF characteristics. The simulations have been performed using the ATLAS 3-D device simulator.

CSDG MOSFET: An Advanced novel architecture for CMOS technology

This paper explores the analog/RF performance of cylindrical surrounding double gate (CSDG) MOSFET in comparison to Cylindrical surrounding Gate (CSG) MOSFET for future nano CMOS devices. CSDG MOSFET has more gates on the silicon substrate to control the channel than any contemporary device. This device has one more cylindrical gate than the CSG MOSFET. That extra gate controls the inner core of the cylindrical silicon substrate. Short Channel Effects (SCEs) parameter like sub-threshold slope (SS), threshold voltage roll-off is shows improved than the CSG MOSFET. Analog /RF performance characteristics like transconductance generation factor gm/Ids, intrinsic gain (gm/gds), Ion/Ioff and effective drain current are calculated for CSG and CSDG MOSFET. Impact of gate dielectric permittivity is also investigated for both MOSFET.

Hot Carrier Reliability Issues of Junctionless Transistor due to Interface Trap Charges for Analog/RF Applications

This paper investigates the analog/RF performance of Junctionless Transistor (JLT) by employing temperature variations, ranging from 200 K to 500 K, along with the influence of interface trap charges. The objective of the present work is to study the performance degradation of junctionless transistor due to interface/fixed trap charges present at the semiconductor/oxide interface of the device at wide temperature ranges. Analog/RF performance distortion in terms of figure of merit (FOM) metrics: intrinsic gain, transconductance, Ion/Ioff ratio, parasitic capacitances, cutoff frequency, current gain, power gain and Gain Transductance Frequency Product (GTFP) has been carried out using ATLAS 3D device simulator. Simulation results reveal that the density of localized charges has strong affects on the device performance and effectively changes the sensitivity of device. It is also analysed that performance degradation is more egregious at low temperature ranges and subthreshold region. This study is beneficial to design and optimization of junctionless device for analog/RF applications.

Effect of ITC on the characteristics of junctionless nanowire transistor(JLNWT) for future ULSI applications: Semianalytical modeling approach

Junctionless Nanowire Transistor (JLNWT) is now being considered one of the most attractive and deserving candidate for future ULSI applications due to its high current driving capability and better SCEs immunity. In this paper, a semi-analytical subthreshold current model has been developed for short channel JLNWT including interface trap charges (ITC) density. This paper explores the electrical performance degradation of JLNWT due to fixed/interface trap charges. Effect of extension, position, density and polarity of interface trap charges are discussed in terms of change in electrical parameters of JLNWT such as central potential, threshold voltage roll-off, subthreshold slope, drain induced barrier lowering and subthreshold current. Impact of technology variation such as channel length, silicon film radius has been carried out in the details. Model verified by using ATLAS 3D device simulator. Results reveal that ITC significantly affects the sensitivity of Junctionless NWT and is more noxious at subthreshold region.