Subhasis Haldar

An accurate charge control model for spontaneous and piezoelectric polarization dependent two-dimensional electron gas sheet charge density of lattice-mismatched AlGaN/GaN HEMTs

Abstract The present paper proposes an improved charge control model of lattice-mismatched AlGaN/GaN HEMTs, valid over the entire operating region. The model for estimation of two-dimensional electron gas (2-DEG) sheet carrier concentration accounts for the strongly dominant spontaneous and piezoelectric polarization at the AlGaN/GaN heterointerface. The dependence of 2-DEG sheet carrier concentration on the aluminum composition and AlGaN layer thickness has been investigated in detail. Current–voltage characteristics developed from the 2-DEG model include the effect of field dependent mobility, velocity saturation and parasitic source/drain resistances. Close proximity with experimental data confirms the validity of the proposed model.

Physics-based analytical modeling of potential and electrical field distribution in dual material gate (DMG)-MOSFET for improved hot electron effect and carrier transport efficiency

We propose a new two-dimensional (2-D) analytical model of a dual material gate MOSFET (DMG-MOSFET) for reduced drain-induced barrier lowering (DIBL) effect, merging two metal gates of different materials, laterally into one. The arrangement is such that the work function of the gate metal near the source is higher than the one near the drain. The model so developed predicts a step-function in the potential along the channel, which ensures screening of the drain potential variation by the gate near the drain. The small difference of voltage due to different gate material keeps a uniform electric field along the channel, which in turn improves the carrier transport efficiency. The ratio of two metal gate lengths can be optimized along with the metal work functions and oxide thickness for reducing the hot electron effect. The model is verified by comparison to the simulated results using a 2-D device simulator ATLAS over a wide range of device parameters and bias conditions.

Analytical model for threshold voltage and I-V characteristics of fully depleted short channel cylindrical/surrounding gate MOSFET

Abstract The present paper proposes an analytical model of threshold voltage and current voltage characteristics for short channel fully depleted cylindrical/surrounding gate MOSFET based on the solution of Poisson’s equation in cylindrical coordinates. The analysis takes into account the field-dependent mobility, velocity saturation and the effect of source/drain resistance. Advantages of surrounding/cylindrical structure over the conventional planar structure are investigated in detail. The results so obtained are in good agreement with simulated data available in the literature.

An analytical drain current model for dual material engineered cylindrical/surrounded gate MOSFET

In this paper, a drain current model incorporating drain-induced barrier lowering (DIBL) has been developed for Dual Material gate Cylindrical/Surrounding gate MOSFET (DMG CGT/SGT MOSFET) and the expressions for transconductance and drain conductance have been obtained. It is shown that DMG design leads to drain current enhancement and reduced output conductance. The effectiveness of DMG design was scrutinized by comparing with single metal gate (SMG) CGT/SGT MOSFET. Moreover, the effect of technology parameters variations workfunction difference has also been presented in terms of gate bias, drain bias, transconductance and drain conductance. Results reveal that the DMG SGT/CGT devices offer superior characteristics as compared to single material gate CGT/SGT devices. A good agreement between modeled and simulated results has also been obtained thus providing the validity of proposed model.

An Investigation of Linearity Performance and Intermodulation Distortion of GME CGT MOSFET for RFIC Design

In this paper, an extensive study on the intermodulation distortion and the linearity of gate-material-engineered cylindrical-gate MOSFET (GME CGT MOSFET) has been done, and the influence of technology variations such as channel length and gate material workfunction variations is explored using an ATLAS 3-D device simulator. The simulation results reveal that the GME CGT MOSFET design displays a significant enhancement in the devices linearity and intermodulation distortion performance in terms of the figure-of-merit metrics VIP2, VIP3, IIP3, and IMD3 and the higher order transconductance coefficients gm1, gm2, and gm3. The results are, thus, useful for optimizing the device bias point for RFIC design with higher efficiency and better linearity performance.

Impact of gate material engineering(GME) on analog/RF performance of nanowire Schottky-barrier gate all around (GAA) MOSFET for low power wireless applications

In this paper Gate Material Engineered (GME) Gate-Stack (GS) silicon nanowire Schottky-Barrier (SB) Gate All Around (GAA) MOSFET and Single Material Gate Stack Schottky-Barrier Source/Drain Gate All Around (SM-GS-SB-S/D GAA) structures are proposed for low- power wireless applications. The Analog/RF performance for wireless applications of these devices are demonstrated. The effect of Schottky-Barrier (Metal) S/D is studied for Single Metal (SM)-SB-GAA, (Dual Metal) DM-SB-GAA, SM-GS-SB-GAA and GME-GS-SB-GAA MOSFETs, and it is found that GME-GS-SB-GAA MOSFET with metal drain source shows much improved performance in terms of transconductance (gm), output conductance (gd), Early Voltage (VEA), Maximum Transducer Power Gain, cut-off frequency (fT), and Ion/Ioff ratio. Further, harmonic distortion for wireless applications is also studied using ATLAS-3D device simulator. Due to low parasitic S/D resistance the metal Source/Drain DM-GS-SB-S/D-GAA MOSFET demonstrates remarkable Ion of~31.8µA/µm and saturation transconductance gm of~68.2µS with improved third order derivative of transconductance gm3. High cut-off frequency of Dual Metal-Schottky Barrier-GAA MOSFET: 193GHz.Highest Ion/Ioff ratio of DM-GS-SB-GAA MOSFET: 9.58×104.High transconductance of DM-GS-SB-GAA MOSFET: 68.2µS.Low power VDS=50mV, with suppressed gm3.Lightly doped channel (NA=1×1016cm-3 ), amalgamation of Dual metal Gate.

Performance Evaluation and Reliability Issues of Junctionless CSG MOSFET for RFIC Design

This paper investigates the reliability issues of junctionless cylindrical surrounding-gate (JL CSG) MOSFET by employing temperature variations, ranging from 200 K to 500 K, along with the influence of interface trap charges. Furthermore, the analog/RF performance evaluation and linearity distortion analysis due to the interface trap charges in terms of figure-of-merit metrics, i.e., drain current Ids; intrinsic gain (gm/gd) Ion/Ioff ; cutoff frequency fT; gain; gain transconductance frequency product; IMD3; VIP2; VIP3; IIP3; and higher order transconductance coefficients gm1, gm2, and gm3 of JL CSG MOSFET have been carried out. A direct comparative study in terms of performance degradation is made between gate material engineered (GME) and single-material gate (SMG) JL CSG MOSFET using ATLAS 3-D device simulator. Simulation results reveal that a GME JL transistor shows better immunity against the influence of interface trap charges and exhibits significant enhancement to maintain device linearization, as compared to an SMG JL CSG MOSFET, so that it can be used as a high-efficiency linear radio-frequency integrated-circuit design and wireless applications. Also from simulation study, degrading effects in JL CSG MOSFET are more pronounce at low temperature and subthreshold region. Apart from analog/RF performance, trap charges change the temperature sensitivity coefficient of the drain current and zero crossover point.

An accurate 2D analytical model for short channel thin film fully depleted cylindrical/surrounding gate (CGT/SGT) MOSFET

The present analysis proposes a 2D analytical model of SGT/CGT MOSFET for potential distribution, short channel threshold voltage and current voltage characteristics. The model takes into account the effect of source/drain resistance, field-dependent mobility, velocity saturation and drain-induced barrier lowering (DIBL) effect. Advantages of SGT/CGT MOSFET over conventional planar structures are analyzed in detail and the results obtained are verified with simulated data.

Comprehensive analysis of small-signal parameters of fully strained and partially relaxed high Al-content lattice mismatched Al/sub m/Ga/sub 1-m/N/GaN HEMTs

Proposes an accurate model to investigate the small-signal microwave parameters of fully strained (FS) and partially relaxed (PR) Al/sub m/Ga/sub 1-m/N/GaN high electron-mobility transistors (HEMTs). It is observed that elastic strain relaxation of the Al/sub m/Ga/sub 1-m/N layer imposes an upper limit on the maximum two-dimensional electron-gas sheet charge density and is, thus, extremely critical in determining the microwave performance of high Al-content Al/sub m/Ga/sub 1-m/N/GaN HEMTs. The model incorporates the effects of strain relaxation of the barrier layer, field-dependent mobility, parasitic source/drain resistance, and velocity saturation to evaluate drain current, transconductance, drain conductance, cutoff frequency, and transit time of FS and PR Al/sub m/Ga/sub 1-m/N/GaN HEMTs with different Al mole fractions. The proposed model predicts a high drain current of 5.94 A/mm for a PR 0.3-/spl mu/m Al/sub 0.4/Ga/sub 0.6/N/GaN HEMT, which is in close proximity with previously published simulated results. A peak transconductance of 154 mS/mm is also estimated for a 1-/spl mu/m gate-length device with aluminum concentration of 15% (FS), which is in close agreement with previously published measured data. A high cutoff frequency of 21.09 GHz was predicted for a 0.6-/spl mu/m device with an Al mole fraction of 0.5 (PR), thus showing the potential of AlGaN/GaN HEMTs for microwave applications.

An analytical subthreshold current modeling of cylindrical gate all around (CGAA) MOSFET incorporating the influence of device design engineering

Abstract An analytical model of CGAA MOSFET incorporating material engineering, channel engineering and stack engineering has been proposed and verified using ATLAS 3D device simulator. A comparative study of short channel effects for various device structures has also been carried out incorporating the effect of drain induced barrier lowering (DIBL), threshold voltage lowering and degradation of subthreshold slope. The effectiveness of applying the three region doping profile concept in the channel such as high-medium-low and low-high-low and its comparison with Gaussian doping profile to the cylindrical GAA MOSFET has been examined in detail. Reduced SCEs have been evaluated in combined designs i.e. TM–GC–GS, GCGS and DM–GC–GS. Out of several design engineering, GC–GS CGAA gives nearly ideal subthreshold slope whereas TM–GC–GS CGAA provides overall superior performance to reduce SCEs in deep nano-meter. The results so obtained are in good agreement with the simulated data which validate the model.