Yoichi Tomo

Novel ARC optimization methodology for KrF excimer laser lithography at low K1 factor

This paper describes a new anti-reflective coating (ARC) optimization methodology, and reports a practical new ARC material and its actual performance for KrF excimer laser lithography as an application of this methodology. First, the optimal optical conditions, refractive index and thickness, for ARC are defined as those values that cause the minimal energy absorption fluctuation for various in a photoresist thicknesses. To find optimal optical conditions, we calculated the energy absorbed in a photoresist for continuously different ARC optical conditions using a multi thin-film interference simulator based on the matrix method for various photoresist thicknesses. As an application results of this method, we show optimal ARC optical conditions, i.e. refractive indices for various thicknesses, for a tungsten silicide (W-Si) substrate, which is highly reflective and the critical layer for KrF excimer laser lithography. Next, we searched for a practical material to be used as an ARC whose refractive indices were closest to the optimal conditions. From these results, we found a novel and practical material for optical lithography. Silicon carbide (SiC) films satisfied optimal optical conditions as an ARC for W-Si substrates. For the swing ratio, a photoresist absorption variation of ±21% without SiC was reduced to less than ±1% with SiC. Finally, in order to achieve an ARC performance on actual structures, we optimized the SiC refractive index as an ARC for W-Si substrates using various ECR Plasma CVD conditions. As a result, we obtained a high performance ARC for W-Si substrates. A critical dimension variation of 0.12pm without SiC was reduced to less than 0.02pm with SiC for 0.35pm L/S.

Practical resolution enhancement effect by new complete antireflective layer in KrF excimer laser lithography

A new complete anti-reflective layer (ARL) for KrF excimer laser lithography, which becomes an excimer laser lithography to a practical mass production tool beyond 0.35 micrometers rule devices, is developed. This new ARL, whose material is a type of hydro silicon oxynitride film (SiOxNy:H), can be applied to tungsten silicide (W-Si) and even to aluminum silicon (Al- Si) substrates by controlling deposition conditions in plasma enhanced chemical vapor deposition systems. Using this SiOxNy:H film with 30 nm and 25 nm thicknesses on W-Si and Al-Si substrates respectively, critical dimension variations for both substrates are drastically reduced to within 0.02 micrometers for 0.30 micrometers imaging. On actual device structures, with these SiOxNy:H film as an ARL, notching effects by halation are completely reduced. Moreover, these SiOxNy:H film can not only be deposited with topographical uniformity but also etched with conventional SiO2 etching conditions. Another advantage with ARL is a depth of focus enhancement effect. With a SiOxNy:H film depth of focus for the critical dimension is enlarged more than 23% for 0.35 micrometers line and space patterns. Accordingly, practical resolution is enhanced. From the above effect, the limitations of KrF excimer laser lithography for ideal substrate conditions are considered from the point of view of optimal projection lens NA for various feature sizes.

Process issue improvement of surface image transfer technique: Depth‐of‐focus characteristics and their comparison with simulation results

There are several disadvantages concerning surface image transfer technique for contact hole fabrication in KrF excimer laser lithography utilizing absorbing photoresist SAL601 (Shipley, chemically amplified negative type). A long development time (MF622, Shipley, 10 min) is the first disadvantage, but this can be improved by using concentrated developer (MF312‐CD38, Shipley) without loss of focus margin. Pattern transfer thicknesses limited to an oxide layer of less than 0.2 μm is the second disadvantage, but this can be improved to a thickness of 0.8 μm by using more anisotropic etching conditions. Small depth of focus (DOF) is the third and the most critical disadvantage, and this can be improved by employing low numerical aperture (NA) and high σ (coherency factor) exposure conditions (NA=0.35, σ=0.9). Comparison between the DOF characteristics for a 0.4 μm contact hole using SAL601 and a two‐dimensional photointensity simulation has resulted in a simple metric to predict the DOF by mask edge intensit...

Improvement of the resist pattern collapse

In this study, we investigated resist pattern collapse during the resist development process. We evaluated the effect of a simple improvement such as rinse-liquid sequencing and rinsing using surfactants. First, we controlled the wafer spinning speed during the rinse-liquid flow step to reduce liquid flow shock. Using this approach, we obtained a 110-nm L/S (line and space) structure with no pattern collapse. However, this technique has only a small effect on preventing pattern collapse with sub-100-nm devices. By using a rinse process with a surfactant, we could control pattern collapse with 100-nm L/S or smaller patterns. Finally, we have succeeded in controlling pattern collapse of 70-nm L/S patterns (aspects ratio of 4.6) using a surfactant during the rinse process. These two simple methods are a significant improvement over conventional rinse processes. These process improvements are available for 90-nm (and smaller) design rules and are applicable for a single layer resists.

Shot number analysis on character projection e-beam lithography for random logic device fabrication at 70-nm node

A reduction efficiency of shot numbers in character projection (CP) electron-beam (EB) lithography with memory device application depends on a design rule (cell size) and a pattern complexity within a memory cell. Many researchers reported that it was approximately 1/10 to 1/100 compared with conventional variable-shaped beam (VSB) method. The reduction of shot numbers in memory devices mainly comes from allowance to place multiple cells in one CP-cell area and simplicity of the cells placement (regular pitch with adjacent allocation). On the other hand, there are few reports concerning reduction efficiency of shot numbers with logic specific application in CP EB lithography due to the complexity of logic cells allocation to CP-cell area. To analyze this, logic device layout data in 70nm node was prepared by shringking actual functional device data of 350 nm node in the ratio of 1/5 and extracting random logic region. The size of this region was 1,094 x 283 micrometers . The height of logic cell was 2.64micrometers and it was smaller than typical one CP-cell size in second aperture (5 x 5micrometers ). The pattern data in GDS-II stream format was converted into EB exposure data: divided figures (rectangles). By this procedure, numbers of figures and cells were obtained. The total number of referred logic cell was 26,812. Among 26,812 cells, only 111 common (unique) logic cells were used for the logic region. The sum of figures in gate layer was 412,251 and this value was assumed to be equal to a total number of shots in conventional VSB method. Among the 111 common cells, only 6 cells in the gate layer showed width more than 5micrometers (maximum CP-cell size). Most frequently referred cell was an inverter and the number of reference was 5,395. The referred frequency of each cell exponentially decreased when the cells were arranged in descending order of reference. Among the total figures, top cell showed 66,120 accumulated number of figures (referred number=2,204, figures in cell=30). The cumulative number of total shots also exponentially decreased when cells were arranged in descending order of total shots. So it is necessary to decide the appropriate maximum number of CP- cell for futur CP EB exposure systems considering the reductoin efficiency of the shot numbers. For the current CP EB exposure tool of Hitachi (HL system), allowed number of CP-cell is 21 which means only 5 different (frequently referred) logic cells can be allocated in CP aperture with typical placement in 4 orientations. But even in this case, total required shot numbers of this logic region for EB Exposure can be reduced to approximately ½. For the ADVANEST CP EB system (allowed number of CP-cell = 100), reduction ratio of shot numbers is 1/4. For the pseudo CP EB system with 500 CP-cells in second aperture, reduction ratio of shot numbers would be 1/15. So, CP EB lithography is one of the promising candidates for small or medium volume production technology especially memory with logic device application after 70 nm node if the maximum number of CP-cell is appropriately increased.

0.35 μm rule device pattern fabrication using high absorption‐type novolac photoresist in single layer deep ultraviolet lithography: Surface image transfer for contact hole fabrication

0.35 μm design rule device patterns were fabricated using high absorption‐type positive and negative photoresist with a KrF excimer laser stepper. The main reason for using high absorption‐type photoresist was to minimize the thin film interference effect caused by high reflectivity of the substrate in the deep ultraviolet region. The positive photoresist was FH‐EX1 (Fuji‐Hunt) and negative photoresist was SAL601. Both contain novolac resin as the base polymer. The positive photoresist was mainly used for poly‐Si and W–Si layer pattern fabrication and the negative photoresist was used for the contact hole pattern fabrication. In the contact hole fabrication a surface image transfer technique was used. This technique relies on the direct transfer of the surface negative photoresist image to the insulating layer with highly anisotropic etching and is completely different from the so‐called ‘‘surface imaging technique’’ using gas phase silylation and successive dry resist development (O2 reactive ion etching...

Defect printability of hole pattern on electron projection lithography

We investigated the defect printability of hole patterns in electron projection lithograpy (EPL) using a diamond reticle with a programmed defect pattern. The reticle was fabricated by NTT-AT and wafer exposure was performemd using Nikons EB projection experimental column. We simulated the defect printability to udnerstand in greater detail. We found that the mask error enhancement factor (MEF) of the size shift defect category exceeded the value of one and was degraded by the amount of beam blur. On the other hand, the printability of the dot defect category was lower than the shift category. In particular, pint hole defects smaller than 100 nm were not printed. However, the defect types of under size shift, truncation, edge intrusion, and corner intrusion (they decreased the opening area), actually increased the defect size because the defect was too small for hole patterns to print. In general, the defect printability of hole patterns depends on the beam blur, and the printed error size at the hole patterns getting larger than the line patterns. We have to pay clsoer attention to the hole pattern defect than to the line patterns.

Dynamic image placement accuracy of a stencil mask

Stencil masks are preferable for EPL (Electron-beam Projection Lithography)from the view point of resolution because it s free from the chromatic aberration caused by the electron energy loss in continuous membrane. However, its mechanical structure poses several concerns. Dynamic image placement (IP)accuracy is one of the essential concerns because patterns on the stencil mask are defined by free-standing Si structures. Moreover the whole pattern areas are supported by fine Si grid structures. The step-and-scan motion of EPL tools is expected to cause dynamic displacements of these fragile structures, which lead to deterioration of resolution, critical dimension (CD)and overlay (OL) accuracies. Two kinds of the dynamic displacements on an EPL stencil mask were estimated by simulations. One is the vibration of the free-standing structures and the other is the dynamic distortion of the whole pattern area. The maximum acceleration of 5 G was assumed in the simulations according to a throughput estimation. The free-standing structures are modeled into cantilever beams and both-end-fixed beams. It was found that the vibration of the structures could be suppressed below the amplitude of 1 nm by limiting the beam length. The limitations were practical ones for complementary split of mask layout. The whole pattern area was modeled into a simple grid structure. It was found that the maximum dynamic displacement was less than 7 nm. The OL accuracy was estimated including those dynamic displacements down to 35 nm node. The results show that the dynamic displacements of the EPL stencil masks would little affect the OL accuracy. The stencil mask is applicable for device fabrication at 70 nm node and below.

Experimental study of electron beam projection lithography mask defect printability

Mask defect printability of electron beam projection lithography (EPL) was investigated. We fabricated EPL chip reticles including programmed defects. The design of these programmed defects was based on semiconductor equipment and materials international (SEMI) standards, but we modified it from the original to a new design for the 100–70 nm node. In our defect printability experiment, Nikon’s electron beam (EB) projection experimental column was used as an exposure tool with those chip reticles. The acceleration voltage of the electron beam was 100 kV. In the case of the “size shift” defects, the correlation between the defect size on the reticle (×1/4) and the critical dimension (CD) change on the wafer is linear and the defect down to 40 nm was printed. Furthermore mask error enhancement factor is nearly equal to 1. This is the advantage of the EPL over the optical lithography. On the other hand, in the case of “dot” defects, defects smaller than 100 nm on the reticle has a small impact on the CD chang...

Resolution limit in character projection e-beam system

Character projection (CP) electron beam (EB) lithography is one of the promising technologies for the fabrication of random logic memory devices with less than 0.13 micrometer design rules. This is because not only the memory but also the logic cell can be allocated in a single CP area. Using CP EB lithography, moderate throughput and accurate CD control can be achieved compared with a variable shaped EB system. However, its resolution is mainly limited by the Coulomb interaction effect of the electron through the EB stencil mask. The Coulomb interaction effect depends on the electron optical column design of EB systems such as beam current, length of interaction, and beam semi-angle. At Selete, we have evaluated in parallel two CP EB direct writing (DW) machines Hitachi and ADVANTEST. This paper describes the resolution limit of these CP EBDW systems. In this study, 1:1 lines and spaces patterns (50% duty: severe Coulomb interaction condition) are evaluated at various current densities. We found that the ultimate resolution is improved by decreasing current density. And also we found that the focus position shifts beyond the wafer plane by increasing current density. Although the larger beam semi-angle can be effective to improve the resolution limit, it is difficult to change the beam semi-angle of existing columns at Selete. So we have simulated this effect by increasing the source diameter, which is equivalent to increasing the beam semi-angle. By comparing the 100 nm lines and spaces simulation results in the diameter of 7.2 micrometer (normal) and 20 micrometer, increasing the beam semi-angle proved to be effective in resolution enhancement if it is accompanied with simultaneous reduction of the lens aberration.