Yoji Kajitani

Space-planning: placement of modules with controlled empty area by single-sequence

The Single-Sequence (simply SS) is a permutation of integers 1, 2, 3,..., n each represents an object placed on a plane without mutual overlapping. An SS represents a system of ABLR-relations (above, below, left-of, right-of) between every pair of integers by SS-to-ABLR rule: if (x,y) is in SS in this order and x y, then x is left-of or below y, respectively. If objects are rooms of a T-junction floorplan of n rooms and integers denote their Abe-orders, the ABLR-relations between rooms are coded to an SS by just reading the rooms in a dual way. This paper will enhance the definition and the fact to the case when the floorplan consists of m( ≥ n) rooms and the ABLR-relations are defined on the focused n of these rooms. Coding, i.e. getting the minimum SS from a given floorplan and decoding, i.e. getting the minimum floorplan from a given SS such that focused n rooms satisfy the ABLR-relations defined through the SS-to-ABLR rule are fixed by linear time algorithms. The first application is in a core technique space-planning in physical design of large systems. It is to suggest global routes to insert empty-rooms to relieve spot congestion, critical-path, crosstalk, unroutable nets, etc. without changing the ABLR-relations among the focused rooms.

How does partitioning matter for 3D floorplanning

The recent hierarchical design framework[8] for 3D floorplan-ning suggests a better performance than previous flat design framework. Under this framework, the layer assignment of the blocks is accomplished by some partitioning algorithms which are assumed to be critical[8]. In this paper, we provide an empirical study on the impact of such partitioning algorithms on the total wire length. By generating various partitions and running our floorplanner based on these partitions, we obtain the statistic of the resultant wire length. We observe that when the design instance has a large number of blocks which are uniformly sized, different partitions with the same cut size lead to roughly the same wire length. By another experiment, we find out that the cut size of the partition has the major influence on the wire length. Therefore, we argue that cut size is a metric good enough for the wire length optimization of 3D floorplanning and suggest that future research focus on other problems such as thermal effect, signal delay, etc.

Equidistance routing in high-speed VLSI layout design

In VLSI system, a certain set of nets is required to propagate their signals within a tolerable skew of delays. Though the delay of the signal on a wire is determined by a complex environment, it is hard to satisfy this requirement unless all the concerned nets are routed within a certain skew of length. This paper approaches this problem by the concept of l-equidistance routing which aims to route the concerned nets by prescribed length l. After a basic technique to route a 1-sink net with prescribed length, an algorithm is presented for the channel routing where sink terminals are on the upper line and source terminals on the bottom lines. The key idea is in the symmetric slant grid interconnect scheme by which the problem is reduced to the ordinary grid routing problem. An algorithm that attains minimum total wire length is presented. Then a solution is given for the case when terminals are on the perimeters on a rectangle. These algorithms are explained on the Euclidean space. But it is shown that a straightforward transformation of the routes to those on the orthogonal grid is possible keeping the property of equidistance. Proposed algorithms were implemented and applied to random data to demonstrate their ability.

On routing fixed escaped boundary pins for high speed boards

Routing for high speed boards is still achieved manually nowadays. There have been some related works in escape routing to solve this problem recently, however a more practical problem is not addressed. Usually the packages/components are designed with or without the requirement from board designers, and the boundary pins are usually fixed or advised to follow when the board design starts. Previous works in escape routing are not likely to be used due to this nature, in this work, we describe this fixed ordering boundary pin escaping problem, and propose a practical approach to solve it. Not only can we have a way to address, we also further plan the wires in a better way to preserve the precious routing resources in the limited number of layers on the board, and to effectively deal with obstacles. our approach has different feature compared with conventional shortest-path-based routing paradigm. In addition, we consider length-matching requirement and wire shape resemblance for high speed signal routes on board. Our results show that we can utilize routing resource very carefully, and can account for the resemblance of nets in the presence of the obstacles. Our approach is workable for board busses as well.

Multi-level placement with circuit schema based clustering in analog IC layouts

This paper aims at developing an automated device-level placement for analog circuit design which achieves comparable quality to manual designs by experts. It extracts a set of clusters from a circuit schema as experts do. We provide a multi-level placement based on the Sequence-Pair by relaxing the shape of clusters from rectangles and allowing boundaries of clusters to be jagged. The quality of placement is evaluated by a multi-objective according to an experts guideline. We adopt a multi-step simulated annealing to balance a trade-off between the objectives. In experiments, we tested the placement for industrial examples. Our tool attained placements better than those by manual on the average by 10.8% and 6.8% with respect to area and net-length, respectively. It also achieved 1/730 layout time compared with the time by manual.

Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts

Our target is automation of analog circuit layout, which is a bottleneck in mixed-signal design. We formulate the layout explicitly considering manufacturing process, and propose an algorithm that consists of simultaneous expression and optimization of placement and routing. The key is that all the cells and wires are represented by rectangles. The algorithm is combined into a commercial tool, and the performance convinced us that the utilization shortens the design time.

A device-level placement with multi-directional convex clustering

A challenge to an automated layout of analog IC starts with the insight into a high quality placement crafted by experts. It has been observed that such a placement comprises clusters corresponding to groups of matched devices and devices are placed faithfully to the drawn schema while the placement is still compacted. This paper proposes a novel device-level placement based on Sequence-Pair which includes an effective representation of clusters extracted from the schema. A key idea is to capture a topological structure of clusters in order to place clusters at as faithful positions to those in the schema. We represent this structure in terms of ABLR-relations which can be translated into Sequence-Pair. In experiments, we tested our algorithm for industrial instances and compared the results with those by manual. We showed that our results were better than manual results by, on average, 12.8% and 18.1% with respect to area and net-length.

Theory of placement by numDAG related with single-sequence, SP, BSG, and O-tree

After BSG and sequence-pair (SP) of the placement codes, a decade has passed with various proposals of new codes and ideas for applications, especially in VLSI physical design. Different in appearance, they are actually proposing generators of ABLR-relations, i.e. above, below, left-of, or right-of relations between two rectangles on a plane to be non-overlapping, together with methodologies how dimensions and peripheral constraints are integrated. This paper proposes another yet simplest generator numDAG which is simply a directed acyclic graph with vertices labelled with distinct numbers. Assuming each vertex representing a rectangle on a plane, an edge (i, j) is featured to imply the property i is left-of j or i is above j according to the edge being incremental or decremental, respectively, with respect to the numbers of end vertices. To demonstrate that the numDAG is the ABLR-relation generating system hierarchically above existing systems, we relate it with single-sequence, H-and V-constraint graph pair, SP, BSG, and O-tree. It is a future problem to find any practical merit by this idea but the contribution is believed in providing a base to the unified theory of constraint-driven placement. Several new ideas and problems are included

Consistent floorplanning with super hierarchical constraints

Sequence-Pair based floorplanning has been revealed its limit of usefulness in VLSI physical design. Among reasons, the key issue is in its being non-hierarchical and indifferent to the preceding step of partitioning. This paper restructure the algorithm by the idea that the partition algorithm produces the constraint that is imposed on the sequence-pair data. The partition algorithm is the one based on the balanced-bipartition that works hierarchically. Thus a new floorplan algorithm that is consistent with the hierarchical partition algorithm is constructed. This is enhanced to include other algorithms that are based on the binary search. Here, a clock-tree synthesis by H-tree is shown to be consistent. Experiments are given to show better achievements in length and wire-density.

A new approach based on LFF for optimization of dynamic hardware reconfigurations

FPGA placement is a two dimensional placement problem. But recent generations of FPGA allow run-time dynamic reconfiguration. We extend another dimension denoting execution time, so the optimization of the dynamic hardware reconfiguration problem becomes a three dimensional rectangle placement problem with spatial and temporal constraints. In this paper, we propose a new deterministic algorithm LFF (less flexibility first principle), which is derived from human accumulated experience and first presented for a two dimensional packing problem, to solve this problem. Good experimental results show that LFF is very effective and promising.