Yong-shik Hwang

MLC PRAM with SLC write-speed and robust read scheme

We have proposed an integrated method to realize MLC PRAM at 45nm technology node and beyond. It includes reset initialization, Toff skew write, and 2bit write to enhance write-and-verify speed, and 3-cell reference scheme to cope with cell variation due to resistance drift and temperature change. Based on the proposed methods, write throughput can be increased up to SLC level with robust read operation.

Process technologies for the integration of high density phase change RAM

Phase change RAM (PRAM) is a promising memory that can solve the problems of conventional memory - scalability, write/read speed and reliability. The process technologies for the integration of high density PRAM are reviewed. The most important challenge of PRAM is the reduction of writing current. Various approaches to reduce the writing current are reviewed and other key factors for the high density PRAM are discussed.

Integration technologies for scalable high density MRAM

We investigate the key factors for scalable high density MRAM. Specifically we examine problems such as large switching field, small sensing margin and writing disturbance following a decrease in size. We demonstrate these problems and suggest several solutions for realizing high density MRAM.

32.3: Distinguished Student Paper: High Efficiency Hybrid PDP

In order to increase the effective yield of secondary electron emission from MgO protective layer, we used carbon nanotubes (CNTs) as a supplementary electron source for plasma discharge of PDP. CNTs were planted on the surface of transparent dielectric layer and coated with MgO in order to induce field emission of electrons under electric field formed during operation of PDP. Luminance and luminance efficiency of the panel with the CNTs were increased significantly, demonstrating a possibility of hybrid PDPs.