Yongqiang Lu

Navigating registers in placement for clock network minimization

The progress of VLSI technology is facing two limiting factors: power and variation. Minimizing clock network size can lead to reduced power consumption, less power supply noise, less number of clock buffers and therefore less vulnerability to variations. Previous works on clock network minimization are mostly focused on clock routing and the improvements are often limited by the input register placement. In this work, we propose to navigate registers in cell placement for further clock network size reduction. To solve the conflict between clock network minimization and traditional placement goals, we suggest the following techniques in a quadratic placement framework: (1) Manhattan ring based register guidance; (2) center of gravity constraints for registers; (3) pseudo pin and net; (4) register cluster contraction. These techniques work for both zero skew and prescribed skew designs in both wirelength driven and timing driven placement. Experimental results show that our method can reduce clock net wirelength by 16% -33% with no more than 0.5% increase on signal net wirelength compared with conventional approaches.

A parasitic extraction method of VLSI interconnects for pre-route timing analysis

For faster timing closure, a parasitic extraction method is developed for the pre-route VLSI design. This method generates virtual route and estimates congestion using the placement information of standard cells, and then extract the interconnect parasitics with the pattern-library method. The techniques of generating parasitic RC tree according to the improved FLUTE algorithm, and capacitance extraction of route segment considering congestion are presented. Experiments are carried out on industrial design cases, whose results show that the proposed method has high computational speed and comparable accuracy as commercial tool.

Useful clock skew optimization under a multi-corner multi-mode design framework

As VLSI technology scales into sub-65nm realm, the complexity of timing optimization is drastically increased by the consideration of power and variations. Even though designers make great efforts during physical design, they are often faced with still heavy timing violations in deep post-routing stages. For the entire design convergence and timing closure, especially under current multi-corner multi-mode design, some more efficient methods need to be invented. In this work, we propose to address such a kind of issue by exploiting useful clock skew, which can help reduce timing violations rapidly. We also add mode/corner metric balancing measurements to make this method more flexible and applicable especially in such deep stages while the CTS is ready. The results indicate that our method can achieve an average improvements of 33.16% on the worst slack (WS) and 75.56% on the total negative slack (TNS), respectively.

Register placement for low power clock network

In modern VLSI designs, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated. In contrast to most of traditional works that handle this problem only in clock routing, we propose to navigate standard cell register placement to locations that enable further less clock routing wirelength and power. To minimize adverse impacts to conventional cell placement goals such as signal net wirelength and critical path delay, the register placement is carried out in the context of a quadratic placement. The proposed technique is particularly effective for the recently popular prescribed skew clock routing. Experiments on benchmark circuits show encouraging results.

Clock network minimization methodology based on incremental placement

In ultra-deep submicron VLSI circuits, clock network is a major source of power consumption and power supply noise. Therefore, it is very important to minimize clock network size. Traditional design methodologies usually let the clock router to undertake the task of clock network minimization independently. Since a clock routing is carried out based on register locations, register placement actually has fundamental influence to a clock network size. In this paper, we propose a new clock network design methodology that incorporates register placement optimization. Given a cell placement result, incremental modifications are performed according to clock skew specifications. The incremental placement change moves registers toward preferred locations that may enable a small clock network size. At the same time, the side-effect to logic cell placement and wire connections is controlled. Experimental results on benchmark circuits show that the proposed methodology can reduce clock network size considerably with limited impact on signal net wirelength and critical path delay.

Combining clustering and partitioning in quadratic placement

Because of the computation complexity of large circuits, the quadratic placement (Q-Place) cannot solve the placement problem fast enough without any preprocessing. In this paper, a method of combining the MFFC clustering and hMETIS partitioning based quadratic placement algorithm is proposed. Experimental results show it can gain good results but consume long running time. In order to cut down the running time, an improved MFFC clustering method (IMFFC) based Q-place algorithm is proposed in this paper. Comparing with the combining clustering and partitioning based method, it is much fast but with a little increase in total wire length.

Navigating Register Placement for Low Power Clock Network Design*This work was supported by Hi-Tech Research & Development (863) Program of China 2002AA1Z1460, the National Natural Science Foundation of China (NSFC) 60476014, Specialized Research Fund for the Doctoral Program of Higher Education: SRFDP-20020003008 and DAC Graduate Scholarship. Some preliminary results of this paper was presented at Asia South Pacific Design Automation Conference (ASPDAC), January, 2005 [17].

With VLSI design development, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated. In contrast to most of traditional works that handle this problem only in clock routing, we propose to navigate standard cell register placement to locations that enable further less clock routing wirelength and power. To minimize adverse impacts to conventional cell placement goals such as signal net wirelength and critical path delay, the register placement is carried out in the context of a quadratic placement. The proposed technique is particularly effective for the recently popular prescribed skew clock routing. Experiments on benchmark circuits show encouraging results.

An effective floorplanning algorithm in mixed mode placement integrated with rectilinear-shaped optimization for soft blocks

Mixed mode placement (MMP) problem can be successfully solved by combining floorplanning and cell based placement according to circuits hierarchy. Floorplanning is the key design stage for achieving optimum performance if virtual blocks (VB: Soft Block) in floorplanning are not restricted to only have rectangular shapes. In this paper, an effective floorplanning algorithm RSF used in MMP is presented to perform the rectilinear-shaped optimization for VBs. Our approach allows VBs to transform into rectilinear shapes without overlaps and selects the optimum shapes for them during topology optimization of normal floorplanning. It is based on the dead-space block assignment and pin allocation during the process of packing. It depends on the theoretic analysis on lower bound of net wire length in half perimeter mode which makes RSF result in shorter total wire length in floorplanning. Applied in MMP, RSF can improve the final performance of MMP.

Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration

Mixed mode placement (MMP) is characterized by a number of same-height standard cells mixed with scattering big blocks in a fixed die. The variety of size and number of blocks introduces challenges to existing algorithms in achieving reasonable solution quality and running time. A new design flow named recursive mixed mode placement (RMMP) is presented in this paper to provide a solution of MMP with this circuits variety of block configuration taken into account. It starts from recursively partitioning circuits to form a tree of virtual blocks in the different condition of the size and number of blocks as well as the logical or physical hierarchy. Then it combines floorplan on block level and quadratic place (Q-place) on cell level to complete the global placement. Our approach takes advantage of combining floorplan and Q-place algorithms to fit the variety of circuits components. The combined approach improves the algorithm efficiency and obtains satisfactory results of MMP in terms of wire length and running time on various industry and academia test cases.

A timing-perspective study on the wire model in placement

Timing-driven placement has been studied for decades. Many algorithms use traditional wire-length-metric wire models and formulations to add timing driven strategies. Few works try to explore the timing potentials from the wire model of placement. Especially in the current sub-45nm era, two nets with the same wire length possibly vary distinctly from the timing property. In this paper, we explore several factors that affect a nets worst delay and average delay in addition to the tradition interconnect wire condition. We hope to employ them in future timing-driven placement. Theoretic analysis and experimental verification are provided as well.