Yoon-Hyuk Lee

Hardware architecture of high-performance digital hologram generator on the basis of a pixel-by-pixel calculation scheme

In this paper we propose a hardware architecture for high-speed computer-generated hologram generation that significantly reduces the number of memory access times to avoid the bottleneck in the memory access operation. For this, we use three main schemes. The first is pixel-by-pixel calculation, rather than light source-by-source calculation. The second is a parallel calculation scheme extracted by modifying the previous recursive calculation scheme. The last scheme is a fully pipelined calculation scheme and exactly structured timing scheduling, achieved by adjusting the hardware. The proposed hardware is structured to calculate a row of a computer-generated hologram in parallel and each hologram pixel in a row is calculated independently. It consists of and input interface, an initial parameter calculator, hologram pixel calculators, a line buffer, and a memory controller. The implemented hardware to calculate a row of a 1920×1080 computer-generated hologram in parallel uses 168,960 lookup tables, 153,944 registers, and 19,212 digital signal processing blocks in an Altera field programmable gate array environment. It can stably operate at 198 MHz. Because of three schemes, external memory bandwidth is reduced to approximately 1/20,000 of the previous ones at the same calculation speed.

Digital holographic video service system for natural color scene

Abstract. We propose a new system that can generate digital holograms using natural color information. The system consists of a camera system for capturing images (object points) and software (S/W) for various image processing. The camera system uses a vertical rig, which is equipped with two depth and RGB cameras and a cold mirror, which has different reflectances according to wavelength for obtaining images with the same viewpoint. The S/W is composed of the engines for processing the captured images and executing computer-generated hologram for generating digital holograms using general-purpose graphics processing units. Each algorithm was implemented using C/C++ and CUDA languages, and all engines in the form of library were integrated in LabView environment. The proposed system can generate about 10 digital holographic frames per second using about 6 K object points.

High-Performance Computer-Generated Hologram by Optimized Implementation of Parallel GPGPUs

We propose a new development for calculating a computer-generated hologram (CGH) through the use of multiple general-purpose graphics processing units (GPGPUs). For optimization of the implementation, CGH parallelization, object point tiling, memory selection for object point, hologram tiling, CGMA (compute to global memory access) ratio by block size, and memory mapping were considered. The proposed CGH was equipped with a digital holographic video system consisting of a camera system for capturing images (object points) and CPU/GPGPU software (S/W) for various image processing activities. The proposed system can generate about 37 full HD holograms per second using about 6K object points.

Scalable hologram video coding for adaptive transmitting service.

This paper discusses processing techniques for an adaptive digital holographic video service in various reconstruction environments, and proposes two new scalable coding schemes. The proposed schemes are constructed according to the hologram generation or acquisition schemes: hologram-based resolution-scalable coding (HRS) and light source-based signal-to-noise ratio scalable coding (LSS). HRS is applied for holograms that are already acquired or generated, while LSS is applied to the light sources before generating digital holograms. In the LSS scheme, the light source information is lossless coded because it is too important to lose, while the HRS scheme adopts a lossy coding method. In an experiment, we provide eight stages of an HRS scheme whose data compression ratios range from 1:1 to 100:1 for each layered data. For LSS, four layers and 16 layers of scalable coding schemes are provided. We experimentally show that the proposed techniques make it possible to service a digital hologram video adaptively to the various displays with different resolutions, computation capabilities of the receiver side, or bandwidths of the network.

A New System Implementation for Generating Holographic Video using Natural Color Scene

In this paper, we propose a new system which can generate digital holograms for natural color scene. The system consists of both a camera system for capturing images and softwares(SWs) for various image processings. The camera system uses a vertical rig with a depth and a RGB camera and a cold mirror which has the different transmittance according to wavelength for obtaining images with the same view point. The S/W is composed by the engines for processing and servicing the captured images and computer-generated hologram (CGH) for generating digital holograms using general-purpose computing on graphics processing unit (GPGPU). Each algorithm was implemented using C/C++ and CUDA languages, and all engines were integrated in LabView environment. The proposed system can generate 10 digital holographic frames per second using about 6K light sources.

ASIC chipset design to generate block-based complex holographic video

In this paper, we propose a new hardware architecture implemented as a very large scaled integrated circuit by using an application-specific integrated circuit technology, where block-based calculations are used to generate holograms. The proposed hardware is structured to produce a part of a hologram in the block units in parallel. A block of a hologram is calculated using an object point, and then the calculation is repeated for all object points to obtain intermediate results that are accumulated to produce the final block of a hologram. This structure can be used to produce holograms of various sizes in real time with optimized memory access. The proposed hardware was implemented using the Hynix 0.18 μm CMOS technology of Magna Chip, Inc., and it has about 448 K gate counts and a silicon size of 3.592  mm×3.592  mm. It can generate complex holograms and operate in a stable manner at a clock frequency of 200 MHz.

A New ASIC Design of Digital Hologram Generation Circuit for 12×12 Block

본 논문에서는 블록 기반으로 홀로그램을 생성할 수 있는 하드웨어의 구조를 제안하고, ASIC (application specific integrated circuit) 환경을 이용하여 VLSI(very large scaled integrated circuit) 회로로 구현하였다. 제안한 하드웨어는 홀로그램 평면의 블록 단 위로 병렬 연산을 수행할 수 있는 구조를 가지고 있다. 한 객체 포인트에 대한 홀로그램 블록의 영향을 독립적으로 연산한 후에 모든 객체 포인트에 대한 결과를 누적하여 홀로그램을 생성하였다. 이러한 구조를 통해서 다양한 크기의 홀로그램을 하드웨어를 이용하여 생성할 수 있으면서 최소의 메모리 접근량을 사용하면서 실시간으로 동작이 가능하도록 하였다. 제안한 하드웨어는 Magna chip의 Hynix 0.18μm CMOS 라이브러리를 이용하여 구현되었고, 실수항과 복소항의 복소 홀로그램을 생성할 수 있다. 제안한 하드웨어는 최대 200MHz에서 안정적으로 동작할 수 있고, 약 876,608개의 게이트 수로 구현되었다.

Digital Hologram Encryption Algorithm using Fresnel Diffraction

This paper is to propose an encryption method for only an allowed user to see the content for a digital hologram, that is a high value-added content. This paper uses a characteristic of Fresnel transform that the object region is concentrated to a relatively small part of the diffraction plane. By encrypting the concentrated part only the region to be encrypted and in turn the amount of data to be encrypted is reduced a lot, which results in an high efficiency with low encryption rate. As the methodology, a digital hologram is first Fresnel transformed for reconstruction and the result is secondly Fresnel transformed to concentrate the energy into the center of the diffraction plane to encrypt the concentrated region only. For the 2nd transform, energy concentration degree is determined by adjusting the diffraction distance and encryption strength is determined by adjusting the scaling factor. For this we analyze the optimal encryption area according to the diffraction distance and the scaling factor. When applying the proposed method with diffraction distance of 20m the object information was visually unrecognizable with the encryption ratio only 0.005% ~ 0.02%.

Arbitrary Viewpoint/Disparity Stereoscopic Image Generation from a Digital Hologram

This paper proposes a method to generate a stereoscopic image pair from a digital hologram by considering the situation that digital hologram data is serviced but the end-user does not have the proper display equipment, etc. We use Fresnel transform as the method to convert a digital hologram into an image. Each image of the stereoscopic image pair uses a part of the given digital hologram and the sizes of the two partial digital holograms for the two images are chosen to be the same. Here, the size of the image is adjusted by the size of the partial digital hologram and the disparity between the pair images is adjusted by the distance between the centers of the two partial hologram. This paper also deals with how to adjust the size and the disparity of the images. In this paper the generated stereoscopic images are implemented as an anaglyphic display type to confirm the feeling of distance by wearing the red-blue glasses.

Hologram Watermarking Using Fresnel Diffraction Model

This paper is to propose an algorithm for digital hologram watermarking by using a characteristic of the Fresnel diffraction model in 2D image. When 2D image is applied Fresnel transform, the result concentrates center region. When applied to a hologram, on the other hand, the result focused diffraction pattern of 2D form. Using this characteristic, to generate diffraction model by applying 2-th Fresnel transform to the hologram. Corner of diffraction model is mark space. This mark space is embedded watermark and extracted watermark. Experimental results showed that all the extracted watermarks after several kinds of attacks (Gaussian blurring, Sharpening, JPEG compression) showed visibilities good enough to be recognized to insist the ownership of the hologram.