Yoshie Kimura

Impact of Transistor Architecture (Bulk Planar, Trigate on Bulk, Ultrathin-Body Planar SOI) and Material (Silicon or III–V Semiconductor) on Variation for Logic and SRAM Applications

The need to enhance transistor performance below 22-nm node has brought in a change in transistor architecture from planar bulk to either ultrathin-body SOI (UTB SOI) or 3-D trigate transistors. Further improvement in transistor performance at sub-7-nm node is likely to require replacement of silicon channel with high-mobility compound semiconductor (III-V) materials. This paper presents a numerical 3-D simulation study of process variation and sidewall roughness/surface roughness effects on 3-D trigate (tapered and rectangular cross sections) on bulk and UTB SOI devices. We also investigate the effects of variation on future III-V trigate transistors using the same 3-D TCAD scheme. The results show that the threshold voltage variation value, ΔVT, in rectangular Si trigate and UTB SOI due to all the variation sources are 13.1 and 24.6 mV, respectively. Moreover, between Si and III-V compound semiconductors, the In0.53Ga0.47As trigate shows 1.5 times lower total ΔVT value making it a promising candidate for Si replacement. A Monte Carlo study of 6T SRAM cell with fin width or body thickness variation show that the 3σ value of read static noise margin [3σ (RSNM)] is least in SRAMs with rectangular Si trigate. This paper also shows that a 6T SRAM cell at different VCC shows that a Si trigate has VCCmin below 0.4 V.

15nm HP patterning with EUV and SADP: key contributors for improvement of LWR, LER, and CDU

This paper discusses the approach for patterning 15nm Half Pitch (HP) structures using EUV lithography combined with Self-Aligned Double Patterning (SADP). A stack composed of a double hard mask, which allows decoupling photoresist transfer and trim, and an α-Si mandrel, which offers better mechanical properties during the mandrel and spacer patterning, is proposed. A break-down study with the patterning steps was performed to investigate the key contributors for improvement of LWR, LER and CDU, targeting integrated solutions with lithography, etch, thin film deposition, and wet cleans for selected applications. Based on the optimization of these key patterning contributors, optimum LWR, LER and CDU at 15nm HP are demonstrated.

The influence of post-etch InGaAs fin profile on electrical performance

The onset of the 22 nm node introduced three dimensional tri-gate transistors into high-volume manufacturing for improved electrostatics. The next generations of fin nMOSFETs are predicted to be InGaAs based. Due to the ternary nature of InGaAs, stoichiometric and structural modifications could affect the electronic properties of the etched fin. In this work we have created InGaAs fins down to 35 nm fin width with atomic surface structure kept nearly identical to that of the bulk. Our experimental and simulation results show the impact of surface stoichiometry and fin profile on electrical performance.

Key contributors for improvement of line width roughness, line edge roughness, and critical dimension uniformity: 15 nm half-pitch patterning with extreme ultraviolet and self-aligned double patterning

Abstract. The approach for patterning 15-nm half-pitch (HP) structures using extreme ultraviolet lithography combined with self-aligned double patterning is discussed. A stack composed of a double hard mask, which allows decoupling photoresist transfer and trim, and an α-Si mandrel, which offers better mechanical properties during the mandrel and spacer patterning, is proposed. A break-down study with the patterning steps was performed to investigate the key contributors for improvement of linewidth roughness (LWR), line-edge roughness (LER), and critical dimension uniformity (CDU), targeting integrated solutions with lithography, etch, thin film deposition, and wet cleans for selected applications. Based on the optimization of these key patterning contributors, optimum LWR, LER, and CDU at 15 nm HP are demonstrated.

Patterning in the era of atomic scale fidelity

Relentless scaling of advanced integrated devices drives feature dimensions towards values which can be expressed in small multiples of the lattice spacing of silicon. One of the consequences of dealing with features on such an atomic scale is that surface properties start to play an increasingly important role. To encompass both dimensional as well as compositional and structural control, we introduce the term “atomic scale fidelity.” In this paper, we will discuss the challenges as well as new solutions to achieve atomic scale fidelity for patterning etch processes. Fidelity of critical dimensions (CD) across the wafer is improved by means of the Hydra Uniformity System. Wafer, chip and feature level atomic scale fidelity such as etch rate uniformity, aspect ratio dependent etching (ARDE) /1/, selectivity and surface damage can be addressed with emerging atomic layer etching (ALE) approaches /2/.