David Hellin

Gate double patterning strategies for 10-nm node FinFET devices

Abstract. Amorphous silicon (a-Si) gates with a length of 20 nm have been obtained in a “line & cut” double patterning process. The first pattern was printed with extreme ultraviolet photoresist (PR) and had a critical dimension (CD) close to 30 nm, which imposed a triple challenge on the etch: limited PR budget, high line width roughness, and significant CD reduction. Combining a plasma pre-etch treatment of the PR with the etch of the appropriate hard mask underneath successfully addressed the two former challenges, while the latter one was overcome by spreading the CD reduction on the successive layers of the stack.

15nm HP patterning with EUV and SADP: key contributors for improvement of LWR, LER, and CDU

This paper discusses the approach for patterning 15nm Half Pitch (HP) structures using EUV lithography combined with Self-Aligned Double Patterning (SADP). A stack composed of a double hard mask, which allows decoupling photoresist transfer and trim, and an α-Si mandrel, which offers better mechanical properties during the mandrel and spacer patterning, is proposed. A break-down study with the patterning steps was performed to investigate the key contributors for improvement of LWR, LER and CDU, targeting integrated solutions with lithography, etch, thin film deposition, and wet cleans for selected applications. Based on the optimization of these key patterning contributors, optimum LWR, LER and CDU at 15nm HP are demonstrated.

The influence of post-etch InGaAs fin profile on electrical performance

The onset of the 22 nm node introduced three dimensional tri-gate transistors into high-volume manufacturing for improved electrostatics. The next generations of fin nMOSFETs are predicted to be InGaAs based. Due to the ternary nature of InGaAs, stoichiometric and structural modifications could affect the electronic properties of the etched fin. In this work we have created InGaAs fins down to 35 nm fin width with atomic surface structure kept nearly identical to that of the bulk. Our experimental and simulation results show the impact of surface stoichiometry and fin profile on electrical performance.

Key contributors for improvement of line width roughness, line edge roughness, and critical dimension uniformity: 15 nm half-pitch patterning with extreme ultraviolet and self-aligned double patterning

Abstract. The approach for patterning 15-nm half-pitch (HP) structures using extreme ultraviolet lithography combined with self-aligned double patterning is discussed. A stack composed of a double hard mask, which allows decoupling photoresist transfer and trim, and an α-Si mandrel, which offers better mechanical properties during the mandrel and spacer patterning, is proposed. A break-down study with the patterning steps was performed to investigate the key contributors for improvement of linewidth roughness (LWR), line-edge roughness (LER), and critical dimension uniformity (CDU), targeting integrated solutions with lithography, etch, thin film deposition, and wet cleans for selected applications. Based on the optimization of these key patterning contributors, optimum LWR, LER, and CDU at 15 nm HP are demonstrated.

Self-aligned quadruple patterning to meet requirements for fins with high density

Over recent decades, continuous reductions in the scale of fieldeffect transistors in accordance with Moore’s law, which states that the number of transistors in an integrated circuit doubles every two years, have enabled continuous increases in device performance and transistor density.1–3 Currently, state-of-theart devices are based on structural elements with dimensions of 7nm or even 5nm (N7/N5). The highest-resolution patterns required for N7/N5 devices are silicon fins with a pitch of 18–28nm and metal layers with a pitch of 24–32nm. These dimensions far exceed the resolution attainable with 193 immersion (193i) lithography. Extreme UV lithography might be an alternative process for the formation of lines and spaces, but is expensive and not entirely ready for use in production.4 To overcome the limitations of lithography, multiple patterning methods—litho-etch or self-aligned multiple patterning— were used in the last four stages of device miniaturization based on nodes of 10–28nm (N10–N28).5, 6 To achieve the specifications for fins in N7/N5 devices, we need a self-aligned quadruple patterning (SAQP) method that provides a critical dimension (CD) of about 7nm, a CD uniformity (CDU) and pitch walk of 0.5nm (3 sigma), and a line width roughness (LWR) and line edge roughness (LER) of 1.4 and 1.2nm, respectively. We have developed a low-cost SAQP method that has the potential to meet these requirements for fins. We started with a 193i lithography pattern with a pitch of 90nm and lines and spaces of 40 and 50nm, respectively, which we transferred onto a mandrel. Then we deposited silicon dioxide (SiO2) spacers by Figure 1. Simulation images of the stages of self-aligned quadruple patterning (SAQP) obtained using Coventor SEMulator3D software show, from left to right: patterning of the first core (brown) onto a mandrel (green); deposition of silicon dioxide (SiO2) (light blue) by atomic layer deposition (ALD); etching of the first spacers; etching of the mandrel to produce the second core; further deposition of SiO2 by ALD; and etching of the second spacers and silicon nitride pad (dark blue). The scale bars represent 30nm.

Gate double patterning strategies for 10nm node FinFET devices

Amorphous silicon (a-Si) gates with a length of 20nm have been obtained in a ‘line & cut’ double patterning process. The first pattern was printed with EUV photoresist and had a critical dimension close to 30nm, which imposed a triple challenge on the etch: limited photoresist budget, high line width roughness and significant CD reduction. Combining a plasma pre-etch treatment of the photoresist with the etch of the appropriate hard mask underneath successfully addressed the two former challenges, while the latter one was overcome by spreading the CD reduction on the successive layers of the stack.

Effect of etch-clean delay time on post-etch residue removal for front-end-of-line applications

The benefits of integrating wet clean with plasma dry etch processes have been investigated. The studied applications included shallow trench isolation (STI), hardmask-based poly-silicon (poly-Si) gate, and nickel silicide (NiSi) contact etch. In particular, the novel technology Confined Chemical Cleaning™ has been evaluated using diluted hydrofluoric acid or an ammonia hydroxide–hydrogen peroxide mixture at short and controlled exposure times on the order of seconds. It was observed that the ability to remove post-etch residues using the same wet clean process diminished with increasing delay time between etch and clean, in the timescale of hours. In addition, a detrimental effect on the electrical performance was observed for the contact application. As shown, applying stronger cleaning conditions is one solution to remove residues (STI and poly-Si gate) or to restore the electrical performance (contact). However, the more aggressive residue removal process resulted in a higher substrate loss. The mecha...

Ultimate edge-placement control using combined etch and lithography patterning optimizations

Continued improvement in pattern fidelity and reduction in total edge placement errors are critical to enable yield and scaling in advanced devices. In this work, we discuss patterning optimization in a combined two-layer process, using ArFi self-aligned double patterned line and EUV via process in a 10nm test vehicle. In prior work (1), we showed the composite correction ability for lithography and etch systems in single layer processes. Here, we expand on the optimization and setup to improve the single layer process, improve the line edge roughness, and look at a second layer via process. The sum of all those optimizations is the edge placement. Here, we describe the fidelity of the final multilayer pattern and the process budget for a two-layer line and via process in terms of total edge placement error (EPE) (2). In the line process, control of mechanical interactions in the resist and etch process significantly improve line width and line edge roughness (LWR/LER), with a net improvement in LWR of 30% measured after develop, and 18% measured after etch. Pitchwalk is improved using cross wafer etch and litho cooptimization to less than 1.0nm 3σ. For the via process, we determine the root distribution of EPE resulting from the core placement errors at lithography and etch. Results on final multilayer pattern uniformity, overlay, and edge placement are shown.

Reducing the impact of etch-induced pattern shift on overlay by using lithography and etch tool corrections

With shrinking design rules, the overall patterning requirements are getting aggressively tighter and tighter. For the 5-nm node and beyond, on-product overlay below 2.5nm is required. Achieving such performance levels will not only need optimization of scanner performance but a holistic tuning of all process steps. In previous work, it has been shown that process-induced pattern asymmetry has significant impact on overlay performance at wafer edge and can be partially compensated by applying high-order scanner corrections or optimizing metrology targets. Today, we present the reduction of process-induced pattern asymmetry in a tunable etch system and demonstrate the related on-product overlay improvement combined with scanner corrections. In our work we utilize etch tools (Lam Kiyo® conductor etch systems) with proprietary edge tuning technology that can be used to reduce the etch-related asymmetry at the wafer edge. In combination to this unique method, we evaluate the impact of high order corrections per exposure field to compensate for process asymmetry at the wafer edge with a state-of-the-art 1.35 NA immersion scanner (NXT:1970Ci). The study is done on dedicated test wafers with 10-nm logic node design. We use angle-resolved scatterometry (YieldStar® S-250), atomic force microscopy, and SEM cross-sections to characterize process asymmetry. We present experimental investigation of the effect of etch tuning and scanner corrections on the pattern shift and the resulting overlay. In particular, we present results showing a reduction of etch-induced pattern shift by 12nm at wafer radius 147mm. Results show that asymmetry can be addressed by both, litho compensation and etch tuning, and bring on-product overlay down to the required level. We discuss the benefit of the correction techniques especially for thick hard mask layers (the pattern shift scales linear with hard mask thickness) and evaluate a combined correction scenario, where preventive etch tuning and feed-back based scanner corrections are used. We conclude that a holistic tuning of all process steps will be required to fulfill overlay requirements of future nodes.

Ultimate intra-wafer critical dimension uniformity control by using lithography and etch tool corrections

With shrinking design rules, the overall patterning requirements are getting aggressively tighter. For the 7-nm node and below, allowable CD uniformity variations are entering the Angstrom region (ref [1]). Optimizing inter- and intra-field CD uniformity of the final pattern requires a holistic tuning of all process steps. In previous work, CD control with either litho cluster or etch tool corrections has been discussed. Today, we present a holistic CD control approach, combining the correction capability of the etch tool with the correction capability of the exposure tool. The study is done on 10-nm logic node wafers, processed with a test vehicle stack patterning sequence. We include wafer-to-wafer and lot-to-lot variation and apply optical scatterometry to characterize the fingerprints. Making use of all available correction capabilities (lithography and etch), we investigated single application of exposure tool corrections and of etch tool corrections as well as combinations of both to reach the lowest CD uniformity. Results of the final pattern uniformity based on single and combined corrections are shown. We conclude on the application of this holistic lithography and etch optimization to 7nm High-Volume manufacturing, paving the way to ultimate within-wafer CD uniformity control.