Johan Vertommen

Performance improvement of self-aligned HfO2/TaN and SiON/TaN nMOS transistors

Abstract Direct-etched HfO2/TaN nMOS transistors were fabricated. The performance of the transistors with aggressively scaled EOT is comparable or better than that of SiO2/poly transistors. The performance enhancement requires a combination of EOT scaling and an appropriate interface layer control. The performance of the direct-etched TaN gated HfO2 based transistors is also compared to the performance of similar TaN gated SiON based transistors. It is observed that for equal gm the leakage is lower for HfO2 based transistors, despite the lower EOT for the HfO2 based devices.

Dry development in an O2/SO2 plasma for sub-0.18 μm top layer imaging processes

Dry development using thin layer imaging (TLI) in either a bilayer approach or top surface imaging are currently investigated as viable alternatives to extend optical lithography to 0.13 μm and below. This article describes a systematic study of dry development in a LAM TCP9400SE inductively coupled plasma etcher for both a single layer TLI resist process and for a bilayer resist process using O2 and SO2/O2 chemistries. The effect of the important machine parameters such as TCP power, bias power, O2 and SO2 gas flows, on the process characteristics (etch rate, selectivity, uniformity, anisotropy) and on the lithographic performance (resolution, profile control, proximity) of a TSI process at 248 has been investigated by means of statistically designed experiments. As line edge roughness (LER) is a critical issue for TSI, the effect of the dry development conditions on LER have been quantified. The effect of temperature on profile control is also presented. In a second part of this article, these trends ha...

Silicon Nano-Pillar Test Structures for Quantitative Evaluation of Wafer Drying Induced Pattern Collapse

Silicon nano-pillars as test structures for quantitative evaluation of advanced wafer drying are presented. The method consists of the use of pillar structures with an aspect ratio up to 28 in combination with top-down SEM inspection and subsequent image analysis for quantification. The test vehicle allows characterizing cleaning techniques by a threshold aspect ratio below which value the features do not collapse. As such, a higher critical aspect ratio corresponds to a superior wetting/drying method. Furthermore, as the metrology is specific and includes cluster size distribution analysis, it can bring new insights in the mechanism of pattern collapse.

45 nm nMOSFET with metal gate on thin SiON driving 1150 /spl mu/A//spl mu/m and off-state of 10nA//spl mu/m

We demonstrate for the first time that nMOS devices with PVD TaN gate on 1.2 nm EOT SiON can be fabricated with high drive currents. On state currents of 1150 /spl mu/A//spl mu/m (I/sub off/ < 10 nA//spl mu/m) at 1.2 V and 810 /spl mu/A//spl mu/m (I/sub off/ < 10 nA//spl mu/m) at 1.0 V are among the highest ever reported. The TaN metal gate electrode allows the capacitance equivalent thickness (CET or T/sub ox-inv/) to be scaled by 0.4 nm without increasing the gate leakage. A special metal etch stopping on 1.4 nm EOT SiON has been developed resulting in gate stacks of similar reliability as poly gate electrodes. We also report on an implant into the metal gate electrode that reduces gate leakage and increases mobility.

30nm half-pitch metal patterning using Moti CD shrink technique and double patterning

Double patterning lithography appears a likely candidate to bridge the gap between water-based immersion lithography and EUV. A double patterning process is discussed for 30nm half-pitch interconnect structures, using 1.2 NA immersion lithography combined with the MotifTM CD shrink technique. An adjusted OPC calculation is required to model the proximity effects of the Motif shrink technique and subsequent metal hard mask (MHM) etch, on top of the lithography based proximity effects. The litho-etch-litho-etch approach is selected to pattern a TiN metal hard mask. This mask is then used to etch the low-k dielectric. The various process steps and challenges encountered are discussed, with the feasibility of this approach demonstrated by successfully transferring a 30nm half-pitch pattern into the MHM.

15nm HP patterning with EUV and SADP: key contributors for improvement of LWR, LER, and CDU

This paper discusses the approach for patterning 15nm Half Pitch (HP) structures using EUV lithography combined with Self-Aligned Double Patterning (SADP). A stack composed of a double hard mask, which allows decoupling photoresist transfer and trim, and an α-Si mandrel, which offers better mechanical properties during the mandrel and spacer patterning, is proposed. A break-down study with the patterning steps was performed to investigate the key contributors for improvement of LWR, LER and CDU, targeting integrated solutions with lithography, etch, thin film deposition, and wet cleans for selected applications. Based on the optimization of these key patterning contributors, optimum LWR, LER and CDU at 15nm HP are demonstrated.

The influence of post-etch InGaAs fin profile on electrical performance

The onset of the 22 nm node introduced three dimensional tri-gate transistors into high-volume manufacturing for improved electrostatics. The next generations of fin nMOSFETs are predicted to be InGaAs based. Due to the ternary nature of InGaAs, stoichiometric and structural modifications could affect the electronic properties of the etched fin. In this work we have created InGaAs fins down to 35 nm fin width with atomic surface structure kept nearly identical to that of the bulk. Our experimental and simulation results show the impact of surface stoichiometry and fin profile on electrical performance.

Key contributors for improvement of line width roughness, line edge roughness, and critical dimension uniformity: 15 nm half-pitch patterning with extreme ultraviolet and self-aligned double patterning

Abstract. The approach for patterning 15-nm half-pitch (HP) structures using extreme ultraviolet lithography combined with self-aligned double patterning is discussed. A stack composed of a double hard mask, which allows decoupling photoresist transfer and trim, and an α-Si mandrel, which offers better mechanical properties during the mandrel and spacer patterning, is proposed. A break-down study with the patterning steps was performed to investigate the key contributors for improvement of linewidth roughness (LWR), line-edge roughness (LER), and critical dimension uniformity (CDU), targeting integrated solutions with lithography, etch, thin film deposition, and wet cleans for selected applications. Based on the optimization of these key patterning contributors, optimum LWR, LER, and CDU at 15 nm HP are demonstrated.

A Novel Concept for Contact Etch Residue Removal

For every new technology node, the specifications for different processing steps become more stringent. For cleaning, one strives to continuously reduce the loss of substrate and film thickness while maintaining a high cleaning efficiency. Short and well-controlled chemical exposure times are desired and may enable the use of more aggressive chemistries. Reducing delay time between etching and subsequent wet clean, by introducing clustered processing, may allow for more effective residue removal. This paper describes a novel cleaning concept, Confined Chemical CleaningTM, and its application in post contact etch residue removal. The technique combines short and controlled exposure times with clustered processing for residue removal.

Scaling of high-k dielectrics towards sub-1nm EOT

High-k dielectric layers are deposited using ALD or MOCVD. Most of the work focused on Hf-based high-k dielectrics, either as pure HfO/sub 2/, as silicate or mixed with Al/sub 2/O/sub 3/. In some cases nitrogen is added to improve the high-temperature stability. Various surface preparation methods and deposition conditions are tested. Compatibility of the high-k stacks with poly-Si and metal electrodes is investigated. Significant improvements in yield and thermal stability are obtained by optimized modifications of the high-k stack. Scaling of the equivalent oxide thickness (EOT) is accomplished by implementing novel ideas in interface engineering and high-k materials processing. High-k stacks are tested in transistor structures with small gate lengths. The origin of the electrical instabilities and the observed drive current degradation of high-k transistors as compared to the SiO/sub 2/ reference transistors are studied in detail.