Hironori Akamatsu

An asymptotically zero power charge-recycling bus architecture for battery-operated ultrahigh data rate ULSI's

An asymptotically zero power charge recycling bus (CRB) architecture, featuring virtual stacking of the individual bus-capacitance into a series configuration between supply voltage and ground, has been proposed. This CRB architecture makes it possible to reduce not only each bus-swing but also a total equivalent bus-capacitance of the ultramultibit buses running in parallel. The voltage swing of each bus is given by the recycled charge-supplying from the upper adjacent bus capacitance, instead of the power line. The dramatical power reduction was verified by the simulated and measured data. According to these data, the ultrahigh data rate of 25.6 Gb/s can be achieved while maintaining the power dissipation to be less than 100 mW, which corresponds to less than 10% that of the previously reported 0.9 V suppressed bus-swing scheme, at V/sub cc/=3.6 V for the bus width of 512 b with the bus-capacitance of 14 pF per bit operating at 50 MHz. >

A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses

A 2-port SRAM cell has to guarantee stability against simultaneously read and write (R/W)-disturbed accesses while keeping cell current (Icell). We verified that it was difficult to provide the stability without any decrease in Icell and any increase in the cell-area penalty only by using the previously proposed techniques for a 1-port cell, and have proposed a new cell biasing technique that controlled the level of the cell VSS (VSSM) with a dual-Vdd and a reduced write-bit-line (WBL) precharge scheme for an 8-transistor (8T) 2-port cell to address the above issue. In this paper, a further consideration was newly demonstrated about the stability for a 2-port SRAM under the random fluctuation of the threshold-voltage (Vth) in 65-nm CMOS technology. The stability with the proposed biasing was compared with that of the conventional cell-Vdd (VDDM) control for write assist. The results under 4-sigma random-Vth fluctuation verified that the minimum Icell at a simultaneously R/W-disturbed cell increased by 2.4 times at Vdd=0.9 V while improving the write margin (WRTM). The cell size based on the same Icell was reduced by 20%. The minimum static noise margin (SNM) was also improved by 44%. Each stability also had the tolerance against 6-sigma random-Vth fluctuation. Furthermore, we have challenged to apply the proposed cell biasing to a 7-transistor (7T) 2-port cell design for area saving with a unique write-assist scheme. The cell size was reduced by 26% with the 7T cell compared with that of the conventional 8T cell. This proposed cell biasing satisfied all the requirements of 2-port SRAM operation while improving stability and saving cell size.

A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations

A 512kb SRAM module is implemented in a 45nm low-standby-power CMOS with variation-tolerant assist circuits against process and temperature. A passive resistance is introduced to the read assist circuit and a divided VDD line is adopted in the memory array to assist the write. Two SRAM cells with areas of 0.245mum2 and 0.327mum2 are fabricated. Measurements show that the SNM exceeds 120mV and the write margin improves by 15% in the worst PVT condition.

A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues

We propose a new 2-port SRAM with a single read bit line (SRBL) eight transistors (8 T) memory cell for a 45 nm system-on-a-chip (SoC). Access time tends to be slower as a fabrication is scaled down because of threshold voltage (Vt) random variations. A divided read bit line scheme with shared local amplifier (DBSA) realizes fast access time without increasing area penalty. We also show an additional important issue of a simultaneous read and write (R/W) access at the same row by using DBSA with the SRBL-8T cell. A rise of the storage node causes misreading. A read end detecting replica circuit (RER) and a local read bit line dummy capacitance (LDC) are introduced to solve this issue. A 128 bit lines - 512 word lines 64 kb 2-port SRAM macro using these schemes was fabricated by a 45 nm bulk CMOS low-standby-power (LSTP) CMOS process technology [1]. The memory cell size is 0.597 mum2. This 2-port SRAM macro achieves 7 times faster access time without misreading.

A Stable SRAM Cell Design Against Simultaneously R/W Disturbed Accesses

A guarantee obligation of keeping the cell-margin against a simultaneously read and write (R/W) disturbed accesses in the same column is required to a 2-port SRAM. We verified that it is difficult to provide these margins without any decrease in cell-current and any increase in cell-area penalty only by using the previously proposed techniques so far. To solve this, we have developed the new cell design technology for an 8-Tr 2-port cell in a 65-nm CMOS technology and have demonstrated that the R/W margins can be improved by 45%/70%, respectively at 0.9V, and the cell-size can be reduced by 20% compared with the conventional column-based Vdd control. Another 7-Tr cell which can reduce cell-area by 31% has been also demonstrated

A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme

The mobile multi-media applications require to lower the operating voltage of embedded SRAMs. The ECC circuit implementation for increasing soft-error and the access timing control that tracks access delay fluctuation in memory core should be considered for the low-voltage operation. A hidden error-check-and-correction (HECC) scheme compensated the access time penalty caused by the ECC logic on the output critical path. And a multi-column ECC word assignment (MCE) increased the multi-bit-error immunity while using only 1-bit-correctable ECC which minimized area penalty. A source-level-adjusted direct sense amplifier (SLAD) and a write-replica circuit with an asymmetrical replica memory cell (WRAM) for the device-fluctuation-tolerant access control were also designed. A 130-nm CMOS 32-Kbit SRAM-macro was fabricated with these circuit techniques, which demonstrated: 1) 0.3-V operation with 6.8 MHz; 2) 30-MHz operation which is feasible for mobile use even at 0.4 V, while keeping 960MHz at 1.5 V; and 3) a reduction by 3.6/spl times/10/sup 5/ in soft-error rate compared with that of conventional ECC.

A 16-Mbit DRAM with a relaxed sense-amplifier-pitch open-bit-line architecture

A 16-Mb dynamic RAM has been designed and fabricated using 0.5- mu m CMOS technology with double-level metallization. It uses a novel trench-type surrounding high-capacitance cell (SCC) that measures only 3.3- mu m/sup 2/ in cell size with a 63-fF storage capacitance. A novel relaxed sense-amplifier-pitch (RSAP) open-bit-line architecture used on the DRAM achieves a high-density memory cell array, while maintaining a large enough layout pitch for the sense amplifier. These concepts allow the small chip that measures 5.4*17.38 (93.85) mm/sup 2/ to be mounted in a 300-mil dual-in-line package with 65-ns RAS access time and 35-ns column address access time. >

0.3 to 1.5V embedded SRAM with device-fluctuation-tolerant access-control and cosmic-ray-immune hidden-ECC scheme

A device-fluctuation-tolerant access-control scheme and a unique cosmic-ray-immune hidden-ECC scheme are implemented in a 32kB SRAM in a 0.13 /spl mu/m CMOS process. The SRAM operates at 0.3V at 6.8MHz under severe device fluctuations. Operation ranges from 30MHz at 0.4V to 960MHz at 1.5V. The hidden-ECC reduces access-timing and the calculated soft-error-rate is reduced by 3.6/spl times/10/sup 10/ per MB.

Gate-over-driving CMOS architecture for 0.5 V single-power-supply-operated devices

A gate over driving CMOS (GO-CMOS) architecture for 100MHz operation at a 0.5V Vdd has been proposed. GO-CMOS manages power delivery to the transistors as follows: (1) instead of using a Vt of -0.1V or less for all transistors, the power supply voltage is boosted for logic circuitry with a small load capacitance, (2) the gate voltage of the driver transistors is boosted to drive the heavily-loaded output nodes. Power is supplied to the driver transistors directly from the external supply to avoid stressing the embedded charge pump circuit. This architecture is used because the measured leakage current using Vt of -0.1V or less is over 10-times that of a GO-CMOS circuit even considering that the boosting efficiency is only 36%. To verify GO-CMOS, a 96kb SRAM test chip used GO-CMOS circuits.

A 256-Mb DRAM with 100 MHz serial I/O ports for storage of moving pictures

A 256-Mb DRAM with refresh-free-FIFO function for storage of moving pictures has been developed using 0.25-/spl mu/m CMOS technology. An operating current of 73 mA (reduction of 52% compared with a conventional circuit) has been achieved at 100 MHz based on introducing (1) a suppressed High(H)-level differential data transfer scheme which ran be operated at 0.6 V, (2) a new pre-charge method which features a 1/2 VCC precharge level in read cycle and VSS pre-charge level in write cycle, and (3) a divided operation of array circuits for serial access. >