Yoshihiro Takao

A 0.11 /spl mu/m CMOS technology with copper and very-low-k interconnects for high-performance system-on-a-chip cores

This paper describes a 0.11 /spl mu/m CMOS technology with high-reliable copper and very-low-k (VLK) (k<2.7) interconnects for high performance and low power applications. Aggressive design rules, 0.11 /spl mu/m gate transistor, and 2.2 /spl mu/m/sup 2/ 6T-SRAM cell are realized by using KrF 248 nm lithography, optical proximity-effect correction (OPC), and gate-shrink techniques. Drain current of 0.63 mA//spl mu/m and 0.28 mA//spl mu/m are realized for nMOSFET and pMOSFET with 0.11 /spl mu/m gate, respectively. Propagation delay of 2-input NAND with the copper/hybrid VLK interconnects is estimated. The delay is improved by more than 70%, compared to 0.18 /spl mu/m CMOS technology with copper/FSG interconnects.

Low-power and high-stability SRAM technology using a laser-recrystallized p-channel SOI MOSFET

Laser recrystallization of p-channel SOI MOSFETs on an undulated insulating layer is demonstrated for SRAMs with low power and high stability. Self-aligned p-channel SOI MOSFETs for loads are stacked over bottom n-channel bulk MOSFETs for both drivers and transfer gates. A sufficient laser power assures the same leakage currents between SOI MOSFETs fabricated on an undulated insulating layer in memory cell regions and on an even insulating layer in field regions. The on/off ratio of the SOI MOSFETs is increased by a factor of 10/sup 4/, and the source-drain leakage current is decreased by a factor of 10-10/sup 2/ compared with those of polysilicon thin-film transistors (TFTs) fabricated by using low-temperature regrowth of amorphous silicon. A test 256-kb SRAM fabricated this technology shows improved stand-by power dissipation and cell stability. The process steps can be decreased to 83% of those TFT load SRAMs if both the peripheral circuit and memory cells are made with p-channel SOI and n-channel bulk MOSFETs. >

A 0.11 μm CMOS technology featuring copper and very low k interconnects with high performance and reliability

Abstract This paper describes a 0.11 μm CMOS technology with high-reliable copper (Cu) and very low k (VLK) (k

Selective Growth of Polyacetylene Narrow Wires Utilizing Capillary Action of Catalyst Solution in Grooves

Polyacetylene narrow wires were selectively grown in SiO2 grooves. A substrate with grooves was held upright and the lower edge was dipped in a pool of the catalyst solution. The solution rised up in the groove by capillary action. A polyacetylene wire 0.1 µm wide, 0.2 µm thick, and 8 mm long was synthesized in a groove 0.2 µm wide and 0.55 µm deep. This length of the wire was limited by that of the grooves. Theoretical calculation shows that the catalyst solution can reach a height of 26 m in this case. Electrical conductivity was 300 S/cm for heavily iodine-doped wires formed in grooves 0.5 µm wide and 0.55 µm deep.