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Yoshimi Egawa

Oki Electric Industry

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Featured researches published by Yoshimi Egawa.

international electron devices meeting | 2006

A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer

Masaya Kawano; S. Uchiyama; Yoshimi Egawa; N. Takahashi; Y. Kurita; Koji Soejima; M. Komuro; S. Matsui; K. Shibata; J. Yamada; M. Ishino; H. Ikeda; Yoshihiro Saeki; Osamu Kato; Hidekazu Kikuchi; Toshiro Mitsuhashi

A 3D packaging technology has been developed for 4 Gbit DRAM. Highly-doped poly-Si through-silicon vias (TSVs) are used for vertical traces inside silicon and interconnection between DRAM chips to realize a DRAM compatible process. Through optimization of the process conditions and layout design, fast poly-Si filling has been obtained. The entire packaging was carried out at the wafer level by using the so-called SMAFTI technology. A new bump and wiring structure for feedthrough interposer (FTI) has also been developed for fine-pitch and low-cost bonding. Simulation of the transfer function of FTI wiring indicated a 3 Gbps/pin data transfer capability

electronic components and technology conference | 2007

A 3D Stacked Memory Integrated on a Logic Device Using SMAFTI Technology

Yoichiro Kurita; Satoshi Matsui; Nobuaki Takahashi; Koji Soejima; Masahiro Komuro; Makoto Itou; Chika Kakegawa; Masaya Kawano; Yoshimi Egawa; Yoshihiro Saeki; Hidekazu Kikuchi; Osamu Kato; Azusa Yanagisawa; Toshiro Mitsuhashi; Masakazu Ishino; Kayoko Shibata; Shiro Uchiyama; Junji Yamada; Hiroaki Ikeda

Archive | 2004

Stacked multi-chip package, process for fabrication of chip structuring package, and process for wire-bonding

Yoshimi Egawa

Archive | 1998

Bond pad for stress releif between a substrate and an external substrate

Shinji Ohuchi; Yoshimi Egawa; Noritaka Anzai

MRS Proceedings | 2006

Development of 3D-Packaging Process Technology for Stacked Memory Chips

Toshiro Mitsuhashi; Yoshimi Egawa; Osamu Kato; Yoshihiro Saeki; Hidekazu Kikuchi; Shiro Uchiyama; Kayoko Shibata; Junji Yamada; Masakazu Ishino; Hiroaki Ikeda; Nobuaki Takahashi; Yoichiro Kurita; Masahiro Komuro; Satoshi Matsui; Masaya Kawano

Archive | 2006

Multi chip package

Yoshimi Egawa

Archive | 2000

Methods for making a plurality of flip chip packages with a wafer scale resin sealing step

Yoshimi Egawa; Kazumi Shinchi; Takeshi Niigaki

Archive | 2006

Through electrode, package base having through electrode, and semiconductor chip having through electrode

Yoshimi Egawa

Archive | 2003

Semiconductor package with a chip connected to a wiring substrate using bump electrodes and underfilled with sealing resin

Yoshimi Egawa; Kazumi Shinchi; Takeshi Niigaki

Archive | 1998

Structure for packaging semiconductor chip

Shinji Ohuchi; Yoshimi Egawa

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Hidekazu Kikuchi

Oki Electric Industry

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Toshiro Mitsuhashi

Oki Electric Industry

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Yoshihiro Saeki

Oki Electric Industry

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Kazumi Shinchi

Oki Electric Industry

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Masaya Kawano

NEC

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Nobuaki Takahashi

NEC

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Osamu Kato

Oki Electric Industry

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Satoshi Matsui

Renesas Electronics

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Shinji Ohuchi

Oki Electric Industry

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Takeshi Niigaki

Oki Electric Industry

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