Masaya Kawano

Fan-Out Wafer-Level Packaging with highly flexible design capabilities

We have developed a new Fan-Out Wafer-Level Packaging (FO-WLP) technology with flexible design capabilities for multilayer fan-out redistribution layers (RDLs) connected to the fine-pitch I/O pads of chips. The prototype of a 2.0 mm × 2.0 mm FO-WLP with 25-pin land grid array (LGA) including a 1.6 mm × 1.6 mm microcontroller chip was fabricated and evaluated. Board-level reliability was also confirmed using 5.0 mm × 5.0 mm FO-WLP. This technology is suited for applications in extremely small microcomputer chip/system packaging for ubiquitous computing.

SMAFTI package with planarized multilayer interconnects

A hybrid multilayer interconnect process and high-throughput die-to-wafer bonding technology were developed and introduced into the SMAFTI (SMArt chip connection with FeedThrough Interposer) package. The fine circuit layer FeedThrough Interposer (FTI) was fabricated between memory and logic dice and offers superior power/signal integrity, allowing over a thousand 3-D inter-chip connections through ultra-fine-pitch feedthrough vias. The unique fabrication processes of the multilayer FTI include a multilayer buildup process on a silicon wafer, filling in vias on the photosensitive polyimide layer, and planarization by chemical mechanical polishing (CMP), resulting in low production costs and an extremely flat surface that ensures void-free die bonding. A simultaneous metal/adhesive bonding process was also evaluated for high-throughput die-to-wafer bonding. Furthermore, the fine interconnect structure was verified to be fundamentally reliable.

System in wafer-level package technology with RDL-first process

We have developed a new system-in-package (SiP) called a “System in Wafer-Level Package” (SiWLP). It is fabricated using “RDL-first” technology for fan-out wafer-level-packages (FO-WLPs) and provides high chip-I/O density, design flexibility, and package miniaturization. We developed this SiWLP by using multilayer RDLs and evaluated its unique packaging processes. We achieved high-throughput fabrication by using die-to-wafer (D2W) bonding with fine-pitch reflow soldering and simultaneous molding/underfilling at the wafer level.

Alternative process and support material for embedded fine-pad-pitch LSI package

Alternative processes have been developed that simplify the fabrication and improve the properties of the “SIRRIUS” package, a direct fan-out package that overcomes the problem of forming connections using flip chip bumps in LSI devices with an increasingly smaller bonding pad pitch and that does not increase the cost of the interposer substrate. Package separation using Cu etchant simplifies fabrication, base plate flatterning using a reverse-warpage apparatus makes the initial Cu base plate virtually flat, and use of an AlSiC base plate makes the SIRRIUS package 35% lighter than one with a Cu base plate. Use of these processes makes the SIRRIUS package even more attractive for the fine-pad-pitch LSI devices expected to replace flip chip ball grid array packages.