Yoshimune Hagiwara

A single chip digital signal processor and its application to real-time speech analysis

A single chip high-performance digital signal processor (HSP) has been developed for speech, telecommunication, and other applications. The HSP uses 3 μm CMOS technology and its architecture features floating point arithmetic and pipeline structure. By adoption of floating point arithmetic, data covering a wide dynamic range (up to 32 bits) can be manipulated. The input clock frequency is 16 MHz, and the instruction cycle time is 250 ns. Efficient signal processing instructions and a large internal memory (program ROM: 512 words; data RAM: 200 words; data ROM: 128 words) make it possible to construct a compact speech analysis circuit by the LPC (PARCOR) method with two HSPs. This paper describes HSP architecture, LSI design, and a speech analysis application.

A 50ns DSP with parallel processing architecture

This report will cover a programmable DSP that avoids I/O bottlenecks through a two-level hierarchy of instructions. The IC contains 430K transistors on a 149mm2die.

A 20-ns CMOS micro DSP core for video-signal processing

A programmable 8-b digital signal processor core with an instruction cycle time of 20 ns is developed. A 37.5-mm chip is fabricated by advanced 1.0- mu m double-level-metal CMOS technology. This processor has a reconfigurable high-speed data path supporting several multiply/accumulate function, including 16-tap linear-phase transversal filtering, high-speed adaptive filtering, and eight-point discrete cosine transformation. To provide high-speed operation within the chip, a programmable phase-locked loop circuit is built on the chip. This circuit generates a high-speed clock, which is a multiple of the system clock fed from outside, and is synchronized to the system clock. >

A Single Chip Digital Signal Processor and Its Application to Real-Time Speech Analysis

A single chip high-performance digital signal processor (HSP) has been developed for speech, telecommunication, and other applications. The HSP uses 3 µm CMOS technology and its architecture features floating point arithmetic and pipeline structure. By adoption of floating point arithmetic, data covering a wide dynamic range (up to 32 bits) can be manipulated. The input clock frequency is 16 MHz, and the instruction cycle time is 250 ns. Efficient signal processing instructions and a large internal memory (program ROM: 512 words; data RAM: 200 words; data ROM: 128 words) make it possible to construct a compact speech analysis circuit by the LPC (PARCOR) method with two HSPs. This paper describes HSP architecture, LSI design, and a speech analysis application.

A single-chip microcomputer with realtime rewritable nonvolatile data storage

An 8b single-chip microcomputer having two nonvolatile NMOS memories, developed for consumer appliance and small industrial system applications will be described. The chip contains both a 1Kbyte program store and a 60byte realtime rewritable data store.

Analysis of error-detecting probability of signature circuit for lsi self-testing and proprosal of new signature circuit

The self-testing method using a multiple-input signature register (MISR) has been proposed as a means of testing logic LSI. This paper analyzes the error-detecting ability when the MISR is used as a pattern compression circuit. Coding theory technique is applied in the analysis. As the first step, assuming that a Hamming code generating polynomial (primitive polynomial) is used as the polynomial in MISR, the error-detection rates are determined theoretically for single through quadruple errors. Then the error-detecting rates for single through quadruple errors are calculated for the modified Hamming code generating polynomial. It is indicated as a result that the multiple error-detection rate, especially the rate for the double error, does not reach 100%. In order to improve the multiple error-detection rate, a reversely dual MISR is proposed in which a pair of MISRs is used with opposite shift directions. When the Hamming code generating polynomial is employed as the polynomial in the reversely dual MISR, it is shown that single and double errors are always detected. The rate of triple error detection is calculated. It is also shown that if the modified Hamming code generating polynominal is used, all single, double and triple errors are detected.

CMOS single-chip digital signal processor

The HSP (HD61810) is a single-chip digital signal processor which includes a high speed arithmetic logic unit, a high speed multiplier, and a large memory on a single silicon chip. Its architecture features floating point arithmetic and a pipeline structure. With the floating point arithmetic operation, the HSP can manipulate a wide dynamic range of data. The instruction cycle of the HSP is 250 ns. One multiply/add operation can be executed per cycle. The HSP uses 3 μm CMOS technology and so achieves low power consumption. It is programmed by an internal instruction ROM.