Kenji Kaneko

A multiprocessor system utilizing enhanced DSPs for image processing

A general-purpose image processor (GPIP) consisting of 64 digital signal processors (DSPs) in a 0.31-m/sup 3/ box is proposed to perform a wide range of image processing tasks. A high-speed DSP called DSP-i has been especially developed for this purpose. It has a highly parallel architecture with a two-level instruction hierarchy, multibank cache, and multiprocessor interface. The DSP-i machine cycle is 50 ns. A novel ring shift register bus architecture offers a flexible structure and an efficient data-exchange method for the system. Along with four proposed operation modes, it cuts the multiprocessing overhead to as little as 20%. The performance of the GPIP is 1000 MOPS (million operations per second).<<ETX>>

A 50ns DSP with parallel processing architecture

This report will cover a programmable DSP that avoids I/O bottlenecks through a two-level hierarchy of instructions. The IC contains 430K transistors on a 149mm2die.

One Chip Servo System LSI for Home VCR

The home VCR is steadily gaining world-wide popu- larity with its high performance and low cost, and now is considered one of the most important home electronic appliances. Since the VCR employs a large number of electronic components, it tends to be quite complicated. To avoid this complication as well as to improve its performance and reliability, its a must to simplify the circuits. The most effective way to achieve this is to reduce the number of components through extensive use of ICs in electronic circuits. Also this approach will be most effective for portable-type VCRs which must be of compact and light-weight design.

A 4.3 ns 0.3 /spl mu/m CMOS 54/spl times/54 b multiplier using precharged pass-transistor logic

A 54/spl times/54 b multiplier with 4.3 ns latency at 2.5 V supply and a 16.96 mm/sup 2/ active area is implemented in 0.3 /spl mu/m CMOS with 6.5 nm gate oxide and four-layer metal. This 4.3 ns latency multiplier is for a floating-point unit (FPU) on a CMOS RISC processor capable of performing IEEE double precision multiply operations in three pipelined stages at 400 MHz (7.5 ns latency and 2.5 ns throughput). This multiplier consists of a 54/spl times/54 b carry-save adder tree and a 108 b carry propagation adder. This multiplier achieves 4.3 ns performance using a modified Wallace tree implemented from 4:2 compressors with precharged pass-transistor circuits, radix-2 Booth encoding with an unbalanced buffer for generating select signals, and a short-path carry-lookahead adder.

An Advanced Bipolar-MOS-I/sub 2/L Technology with a Thin Epitaxial Layer for Analog-Digital VLSI

A novel Bi-MOS technology, Advanced Bipolar CMOS (ABC), is proposed. Bipolar transistors (n-p-n, p-n-p, I/sup 2/L)and MOS transistors (both n- and p-channel) have been successfully fabricated on the same chip with no decrease in performance by using a 3-/spl mu/m design rule. Thin epitaxial layer (<= 2 /spl mu/m) is used in order to obtain small-size high-performance (3-GHz) bipolar devices. Device size is reduced by using a shallow junction and self-aligning technique. n-channel MOS transistors are formed in p-well regions designed to reach p-type substrate, and p-channel MOS transistors are formed in epitaxial layer with an n/sup +/ buried layer. This technology has the potential for monolithic multifunctional analog-digital VLSI.

An untrimmed DAC with 14b resolution

A monolithic 14b D/A converter which is self-compensated without trimming analog components will be described. The device has been fabricated with analog compatible I²L technology, affording a linearity error within<tex>± 1/2</tex>LSB or± 0.003%.

Four A/D LSIs for a portable VCR system

This paper will discuss a set of four bipolar A/D circuits for a hand-held VCR. Used are combinations of analog compatible I2L complementary Schottky transistor logic operated at 40MHz, polyimide multilayer interconnection and precision ion-implanted resistors.