Yoshinobu Yamagami

A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications

In sub-100-nm generation, gate-tunneling leakage current increases and dominates the total standby leakage current of LSIs based on decreasing gate-oxide thickness. Showing that the gate leakage current is effectively reduced by lowering the gate voltage, we propose a local dc level control (LDLC) for SRAM cell arrays and an automatic gate leakage suppression driver (AGLSD) for peripheral circuits. We designed and fabricated a 32-kB 1-port SRAM using 90-nm CMOS technology. The six-transistor SRAM cell size is 1.25 /spl mu/m/sup 2/. Evaluation shows that the standby current of 32-kB SRAM is 1.2 /spl mu/A at 1.2 V and room temperature. It is reduced to 7.5% of conventional SRAM.

A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses

A 2-port SRAM cell has to guarantee stability against simultaneously read and write (R/W)-disturbed accesses while keeping cell current (Icell). We verified that it was difficult to provide the stability without any decrease in Icell and any increase in the cell-area penalty only by using the previously proposed techniques for a 1-port cell, and have proposed a new cell biasing technique that controlled the level of the cell VSS (VSSM) with a dual-Vdd and a reduced write-bit-line (WBL) precharge scheme for an 8-transistor (8T) 2-port cell to address the above issue. In this paper, a further consideration was newly demonstrated about the stability for a 2-port SRAM under the random fluctuation of the threshold-voltage (Vth) in 65-nm CMOS technology. The stability with the proposed biasing was compared with that of the conventional cell-Vdd (VDDM) control for write assist. The results under 4-sigma random-Vth fluctuation verified that the minimum Icell at a simultaneously R/W-disturbed cell increased by 2.4 times at Vdd=0.9 V while improving the write margin (WRTM). The cell size based on the same Icell was reduced by 20%. The minimum static noise margin (SNM) was also improved by 44%. Each stability also had the tolerance against 6-sigma random-Vth fluctuation. Furthermore, we have challenged to apply the proposed cell biasing to a 7-transistor (7T) 2-port cell design for area saving with a unique write-assist scheme. The cell size was reduced by 26% with the 7T cell compared with that of the conventional 8T cell. This proposed cell biasing satisfied all the requirements of 2-port SRAM operation while improving stability and saving cell size.

A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations

A 512kb SRAM module is implemented in a 45nm low-standby-power CMOS with variation-tolerant assist circuits against process and temperature. A passive resistance is introduced to the read assist circuit and a divided VDD line is adopted in the memory array to assist the write. Two SRAM cells with areas of 0.245mum2 and 0.327mum2 are fabricated. Measurements show that the SNM exceeds 120mV and the write margin improves by 15% in the worst PVT condition.

A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues

We propose a new 2-port SRAM with a single read bit line (SRBL) eight transistors (8 T) memory cell for a 45 nm system-on-a-chip (SoC). Access time tends to be slower as a fabrication is scaled down because of threshold voltage (Vt) random variations. A divided read bit line scheme with shared local amplifier (DBSA) realizes fast access time without increasing area penalty. We also show an additional important issue of a simultaneous read and write (R/W) access at the same row by using DBSA with the SRBL-8T cell. A rise of the storage node causes misreading. A read end detecting replica circuit (RER) and a local read bit line dummy capacitance (LDC) are introduced to solve this issue. A 128 bit lines - 512 word lines 64 kb 2-port SRAM macro using these schemes was fabricated by a 45 nm bulk CMOS low-standby-power (LSTP) CMOS process technology [1]. The memory cell size is 0.597 mum2. This 2-port SRAM macro achieves 7 times faster access time without misreading.

A 90 nm low power 32 K-byte embedded SRAM with gate leakage suppression circuit for mobile applications

In sub 100 nm generation, gate tunneling leak current increases and dominates total standby leak current of LSI based on decreasing gate oxide thickness. We propose reducing gate leak current in SRAM using Local DC Level Control (LDLC) and an Automatic Gate Leakage Suppression Driver to reduce gate leak current in the peripheral circuit. We designed and fabricated a 32 KB 1-port SRAM using 90 nm CMOS technology. The 6T-SRAM-cell size is 1.25 /spl mu/m/sup 2/. Evaluation showed that the standby current of 32 KB SRAM is 1.2 /spl mu/A at 1.2 V and room temperature. It is reduced to 7.5% of conventional SRAM.

A Stable SRAM Cell Design Against Simultaneously R/W Disturbed Accesses

A guarantee obligation of keeping the cell-margin against a simultaneously read and write (R/W) disturbed accesses in the same column is required to a 2-port SRAM. We verified that it is difficult to provide these margins without any decrease in cell-current and any increase in cell-area penalty only by using the previously proposed techniques so far. To solve this, we have developed the new cell design technology for an 8-Tr 2-port cell in a 65-nm CMOS technology and have demonstrated that the R/W margins can be improved by 45%/70%, respectively at 0.9V, and the cell-size can be reduced by 20% compared with the conventional column-based Vdd control. Another 7-Tr cell which can reduce cell-area by 31% has been also demonstrated

A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme

The mobile multi-media applications require to lower the operating voltage of embedded SRAMs. The ECC circuit implementation for increasing soft-error and the access timing control that tracks access delay fluctuation in memory core should be considered for the low-voltage operation. A hidden error-check-and-correction (HECC) scheme compensated the access time penalty caused by the ECC logic on the output critical path. And a multi-column ECC word assignment (MCE) increased the multi-bit-error immunity while using only 1-bit-correctable ECC which minimized area penalty. A source-level-adjusted direct sense amplifier (SLAD) and a write-replica circuit with an asymmetrical replica memory cell (WRAM) for the device-fluctuation-tolerant access control were also designed. A 130-nm CMOS 32-Kbit SRAM-macro was fabricated with these circuit techniques, which demonstrated: 1) 0.3-V operation with 6.8 MHz; 2) 30-MHz operation which is feasible for mobile use even at 0.4 V, while keeping 960MHz at 1.5 V; and 3) a reduction by 3.6/spl times/10/sup 5/ in soft-error rate compared with that of conventional ECC.

0.3 to 1.5V embedded SRAM with device-fluctuation-tolerant access-control and cosmic-ray-immune hidden-ECC scheme

A device-fluctuation-tolerant access-control scheme and a unique cosmic-ray-immune hidden-ECC scheme are implemented in a 32kB SRAM in a 0.13 /spl mu/m CMOS process. The SRAM operates at 0.3V at 6.8MHz under severe device fluctuations. Operation ranges from 30MHz at 0.4V to 960MHz at 1.5V. The hidden-ECC reduces access-timing and the calculated soft-error-rate is reduced by 3.6/spl times/10/sup 10/ per MB.

A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues

We propose a new 2port (2P) SRAM with an 8T single-bit-line (SBL) memory cell for 45 nm SOCs. Access time tends to be slower as the device size is scaled down because of the random threshold-voltage variations. The Divided read Bit line scheme with Shared local Amplifier (DBSA) realizes fast access time without increasing area penalty. We also show an additional important issue of a simultaneous Read and Write (R/W) access at the same row by using DBSA with the 8 T-SBL memory cell. A rise of the storage node voltage causes the misreading. The Read End detecting Replica circuit (RER) and the Local read bit line with Dummy Capacitance (LDC) are introduced to solve this issue. A 128 BLtimes512WL 64Kb 2P-SRAM macro which cell size is 0.597mum2 using these schemes was fabricated by 45 nm LSTP CMOS process.

A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses

A guarantee obligation of keeping a Static-Noise-Margin (SNM), a Write-Margin (WRTM), and a cell current (Icell) even against a simultaneous Read/Write (R/W) disturbed access at the same column is required for a 1R/1W (1R/1W) SRAM. We have verified that it is difficult for the previously proposed techniques [1]-[5] so far to meet all the requirements simultaneously without any decrease in Icell or any significant area penalty. In order to address this issue, a new cell design technique for the 1R/1W SRAM cell with 8Trs has been proposed and demonstrated in a 65 nm CMOS technology. It has been shown that Icell in the R/W disturbed column can be increased by 77% and 195% at V dd =0.9 V and 0.6 V, respectively, and a cell size can be reduced by 15%, compared with the conventional column-based cell power-terminal bias (VDDM) control [1], [2] assuming that the same Icell of 9 μA at V dd =0.9 V has to be provided. Compared with the conventional scheme, it has been found that the proposed Write-Bit-Line precharge level (VWBL) control and column-based cell source-terminal bias (VSSM) control can provide a 1.45-times larger SNM for Write-Word-Line (WWL) disturbed cells and a 1.7-fold larger WRTM while keeping the same Icell, respectively.