Katsuji Satomi

A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses

A 2-port SRAM cell has to guarantee stability against simultaneously read and write (R/W)-disturbed accesses while keeping cell current (Icell). We verified that it was difficult to provide the stability without any decrease in Icell and any increase in the cell-area penalty only by using the previously proposed techniques for a 1-port cell, and have proposed a new cell biasing technique that controlled the level of the cell VSS (VSSM) with a dual-Vdd and a reduced write-bit-line (WBL) precharge scheme for an 8-transistor (8T) 2-port cell to address the above issue. In this paper, a further consideration was newly demonstrated about the stability for a 2-port SRAM under the random fluctuation of the threshold-voltage (Vth) in 65-nm CMOS technology. The stability with the proposed biasing was compared with that of the conventional cell-Vdd (VDDM) control for write assist. The results under 4-sigma random-Vth fluctuation verified that the minimum Icell at a simultaneously R/W-disturbed cell increased by 2.4 times at Vdd=0.9 V while improving the write margin (WRTM). The cell size based on the same Icell was reduced by 20%. The minimum static noise margin (SNM) was also improved by 44%. Each stability also had the tolerance against 6-sigma random-Vth fluctuation. Furthermore, we have challenged to apply the proposed cell biasing to a 7-transistor (7T) 2-port cell design for area saving with a unique write-assist scheme. The cell size was reduced by 26% with the 7T cell compared with that of the conventional 8T cell. This proposed cell biasing satisfied all the requirements of 2-port SRAM operation while improving stability and saving cell size.

A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations

A 512kb SRAM module is implemented in a 45nm low-standby-power CMOS with variation-tolerant assist circuits against process and temperature. A passive resistance is introduced to the read assist circuit and a divided VDD line is adopted in the memory array to assist the write. Two SRAM cells with areas of 0.245mum2 and 0.327mum2 are fabricated. Measurements show that the SNM exceeds 120mV and the write margin improves by 15% in the worst PVT condition.

An on-chip high-efficiency and low-noise DC/DC converter using divided switches with current control technique

An on-chip DC/DC converter with high efficiency and low-noise and easy implementation in LSIs is needed for single-supply voltage and low-power operation of LSIs. To obtain high-efficiency, fixed pulse-width modulation (PWM) and zero volt switching (ZVS) adaptive control are used. Operation with efficiency >90% is reported. However, these reports do not discuss low- noise switching operation and easy implementation. These are the most important points for practical use. The specifications for the DC/DC converter are: (1) easy implementation into LSIs as an on-chip DC/DC converter; (2) efficiency over 90% (at Io=80 mA, 3.0 V->2.0 V); (3) output noise below 30 mVp-p. A DC/DC converter which has both efficiency over 92% and 15 mV output noise is incorporated into an LSI.

A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues

We propose a new 2-port SRAM with a single read bit line (SRBL) eight transistors (8 T) memory cell for a 45 nm system-on-a-chip (SoC). Access time tends to be slower as a fabrication is scaled down because of threshold voltage (Vt) random variations. A divided read bit line scheme with shared local amplifier (DBSA) realizes fast access time without increasing area penalty. We also show an additional important issue of a simultaneous read and write (R/W) access at the same row by using DBSA with the SRBL-8T cell. A rise of the storage node causes misreading. A read end detecting replica circuit (RER) and a local read bit line dummy capacitance (LDC) are introduced to solve this issue. A 128 bit lines - 512 word lines 64 kb 2-port SRAM macro using these schemes was fabricated by a 45 nm bulk CMOS low-standby-power (LSTP) CMOS process technology [1]. The memory cell size is 0.597 mum2. This 2-port SRAM macro achieves 7 times faster access time without misreading.

A Stable SRAM Cell Design Against Simultaneously R/W Disturbed Accesses

A guarantee obligation of keeping the cell-margin against a simultaneously read and write (R/W) disturbed accesses in the same column is required to a 2-port SRAM. We verified that it is difficult to provide these margins without any decrease in cell-current and any increase in cell-area penalty only by using the previously proposed techniques so far. To solve this, we have developed the new cell design technology for an 8-Tr 2-port cell in a 65-nm CMOS technology and have demonstrated that the R/W margins can be improved by 45%/70%, respectively at 0.9V, and the cell-size can be reduced by 20% compared with the conventional column-based Vdd control. Another 7-Tr cell which can reduce cell-area by 31% has been also demonstrated

A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues

We propose a new 2port (2P) SRAM with an 8T single-bit-line (SBL) memory cell for 45 nm SOCs. Access time tends to be slower as the device size is scaled down because of the random threshold-voltage variations. The Divided read Bit line scheme with Shared local Amplifier (DBSA) realizes fast access time without increasing area penalty. We also show an additional important issue of a simultaneous Read and Write (R/W) access at the same row by using DBSA with the 8 T-SBL memory cell. A rise of the storage node voltage causes the misreading. The Read End detecting Replica circuit (RER) and the Local read bit line with Dummy Capacitance (LDC) are introduced to solve this issue. A 128 BLtimes512WL 64Kb 2P-SRAM macro which cell size is 0.597mum2 using these schemes was fabricated by 45 nm LSTP CMOS process.

A Stable SRAM Mitigating Cell-Margin Asymmetricity with A Disturb-Free Biasing Scheme

The logic operating voltage is required to suppress for the battery-operated slow application, while the minimum operating voltage of SRAM increase due to the increase in the random threshold-voltage (Vt) fluctuation of the cell transistor (Tr) and the memory capacitance embedded in SoCs with scaling. To suppress the random Vt fluctuation and to guarantee the stable operation over the large memory capacitance at low voltage, a reduced-Vt (LVt) SRAM cell has been proposed. The random Vt fluctuation was suppressed by the proposed LVt cell (Vt = 150 mV) and increase the static noise margin (SNM) for the data-retention at low voltage compared with conventional higher Vt cell (Vt = 300 mV). Another unique disturb-free biasing scheme has also been proposed to cancel the substantial trade-off relationship between SNM and the write margin (WRTM) of SRAM cell. With a 45-nm CMOS technology, these proposed techniques improved the SNM over 6-sigma random Vt fluctuation with the 0.5-V data-retention voltage and the 0.7-V logic bias voltage. Operating current was reduced by 31% at 32-Kbit SRAM module.