Yoshinori Okajima

A 256 Mb SDRAM using a register-controlled digital DLL

This 256 Mb synchronous DRAM with 1 ns clock access is stable against temperature, voltage, and process variation by use of an innovative register-controlled delay locked loop (RDLL). Unlike most conventional high-density DRAMs, the bit-lines are placed above the storage capacitors in this DRAM to relax design rules of the core area. The noise issues are analyzed and resolved to help implement the technology in mass production of 0.28 to 0.24 /spl mu/m 200 MHz DRAMs.

64Kb ECL RAM with redundancy

A 64Kw x l b bipolar ECL RAM with two-array redundancy will be described. This device, using a PNP load cell, was fabricated in IOP-I1 (second generation of Isolation by Oxide and Polysilicon) and 1 . 2 ~ lithography. A redundant circuit configuration was applied to the RAM, without deterioration of the high speed characteristics of ECL. Decoder circuits with jun,ction shorting PROM, can be reliably programmed, and enhance yield, as much as the present.16Kb ECL RAM. Two spare arrays were prepared for row and column; Figure 1. The speed of the spare arrays for decoding has been found to be equivalent to that provided by ordinary decoders, because the only dc high or low voltages to the compare gates are generated by the PROM circuit. But this additional redundant circuit increases the number of peripheral gates and the power dissipation. To overcome this problem, the following circuits were introduced: ( I ) a low power second stage column decoder (most of the unselected driver gates do not require current flow for low output levels); (2) a Darlington word driver with pull down resistance (the high current gain of the Darlington transistor decreases the power of word driver gates); Figure 2. The PNP load cell, includes a P-type deep emitter and collector for fast write switching: additionally, the cell affords control of the beta of the read/write transistor for a decrease of the parasitic sink current’. These diffusions have been merged into a single P-type step (Figure 3) which shortens masking steps and reduces cell area. Fine line 1.2p lithography has also been employed. The minimum emitter size is 1 .21 x 2.41 and the minimum linewidth plus spacing of the first and second metal layers are 4 . 0 ~ and 5 . 0 ~ respectively. Isolation width is 2.4F Cell area is 52412, while die size is 55.4mm2. A typical address access time of lOns has been obtained. Figure 4 shows switching waveforms of the address input and data output. A microphotograph of the chip is shown in Figure 5. Characteristic features of this RAM and typical transistor parameters are summarized on Tables 1 and 2. By applying 1.01 lithography, sub lOns performance is expected.

A 6.5 ns 1 Mb BiCMOS ECL SRAM

A 256 K-word*4-b emitter-coupled-logic (ECL) RAM fabricated by means of 0.8- mu m BiCMOS technology is described. The memory has an address access time of 6.5 ns with active power dissipation of 800 mW at 80 MHz. The memory utilizes a 41- mu m/sup 2/ NMOS four-transistor memory cell, 2-row and 16-column redundancy, a wired-OR sense amplifier, and an improved ECL CMOS level converter to achieve 6.5-ns access time with an ECL 10 K interface. To improve yield for a high-density RAM, a flexible redundancy scheme is necessary. The 2-row and 16-column redundant array increases the number of usable devices at least fivefold compared with a previously reported scheme.<<ETX>>

Performance optimization of BiCMOS circuits under reduced supply voltage

As the supply voltage is reduced, the speed superiority of BiCMOS over CMOS may be diminished, but BiCMOS still has the advantage of inducing relatively smaller characteristic degradation in nMOS transistors by suppressing the drain voltage in the gate. Introducing a new quantitative methodology to evaluate hot electron-induced degradation of nMOS transistor characteristics, this report finds that both BiNMOS gates and CBiMOS gates will have a considerable superiority over CMOS gates in the voltage range from 2.5 V to 3.3 V, even with the same nMOS transistor characteristics. BiNMOS is 30% faster than CMOS owing to amplification of the pMOS drain current by an npn transistor. CBiCMOS is 40% faster and has a sevenfold longer life than CMOS. The speed improvement comes from amplification of both pMOS and nMOS drain currents by npn and pnp transistors, respectively, and the lifetime improvement is due to the effect of the voltage drop through the pnp transistors on the drain terminal of the nMOS transistors. The analytical methodology was also utilized to choose an optimum drain structure, although CMOS necessitates the LDD (lightly doped drain), SD (single drain) structure. Thus, the speed of the gates can be further improved, and the speed of CBiCMOS is expected to be 45% faster than that of CMOS gates. Even in the case of SD structure, the lifetime of CBiCMOS was estimated to be two orders of magnitude longer than that of CMOS with LDD structure.