Yoshinori Shishida

Influence of CMP Chemicals on the Properties of Porous Silica Low-k Films

This paper describes the influence of the chemical mechanical polishing (CMP) process on the degradation in the leakage currents and dielectric constants of porous silica low-k films. It is found that the leakage current and dielectric constant increased by post-CMP cleaning solution due to the increase of CH x and OH bonds according to Fourier transform infrared (FTIR) absorption. This is because the surfactant in the post-CMP cleaning solution permeated into the porous silica. The permeated surfactant in the porous silica can be removed by rinsing with 2-propanol or ethanol after the CMP process. Degradations of the leakage current density and dielectric constant can be recovered by ethanol rinse and subsequent 1,3,5,7-tetramethyl-cyclo-tetrasiloxane vapor treatment, which makes the pore wall surfaces hydrophobic.

Plasma-Enhanced-Polymerization Thin-Film as a Drift Barrier for Cu Ions

The barrier properties of divinyl siloxane-benzocyclobutene (DVS-BCB) films formed by plasma-enhanced polymerization were studied for ultralow-k porous silica (po-SiO) interlayer dielectrics. Time-dependent dielectric breakdown (TDDB) measurements of blanket Cu/BCB/Si metal–insulator–semiconductor (MIS) capacitors showed no polarity dependence of the bias-temperature stresses at 200 °C under 2 MV/cm, indicating that Cu ions hardly drifted into the BCB film with the positive bias stress. On the other hand, Cu/SiOC/Si MIS capacitors under the positively biased Cu showed a significant degradation in the TDDB lifetime compared with the negative bias case. The barrier effect of the thin BCB was confirmed from the TDDB measurements using Cu/BCB/ultralow-k-po-SiO/Si stacked MIS structures. The TDDB lifetime of the stacked MIS capacitor was improved more than 30-fold by the use of 15-nm-thick BCB on po-SiO. The electric field and temperature dependences of the TDDB lifetime of the stacked MIS structure indicated that the TDDB lifetime of po-SiO capped with 15-nm-thick BCB is longer than 10 years at 125 °C and 1.4 MV/cm. We conclude that the barrier property of BCB that is as thin as 15 nm is effective for preventing Cu ion drift into interlayer dielectrics.

Recovery Processes of CMP-Induced Damages for Copper/Porous Silica Damascene Interconnects

This paper describes the effects of recovery processes for the degradation caused by chemical mechanical polishing (CMP) in the integration of Cu/porous silica low-k material interconnects (Cu/po-SiO), in which SiOC is used as CMP-Cap film (Cap-SiOC) for po-SiO film. The leakage current and capacitance between Cu damascene interconnects increased when Cap-SiOC was removed by CMP and the po-SiO was exposed, because the surfactant in CMP chemicals penetrated the po-SiO and the hydrophobicity of the po-SiO decreased, resulting in the increase of water absorption in the po-SiO. As a result of the recovery process after CMP, the leakage current has decreased by three orders of magnitude by applying an isopropyl alcohol rinse and 1,3,5,7-tetramethyl-cyclo-tetrasiloxane (TMCTS) gas treatment, and the capacitance has decreased by 15% by applying the TMCTS gas treatment.

CoWP as a Drift Barrier for Cu Ions Studied by Electric Measurements

Electrical characteristics of self-aligned cobalt-tungsten-phosphide (CoWP) as a copper (Cu) drift barrier for advanced Cu interconnects were investigated using blanket Al/SiO 2 /CoWP/Cu metal-insulator-metal (MIM) structures. The time-dependent dielectric breakdown measurements of the MIM structure under the bias-temperature stress tests demonstrated that the median time-to-failure (MTF) of chemical-vapor-deposited SiO 2 improves by more than 20 times by forming a 10 nm thick CoWP. The improved MTF is comparable to that measured with the reversed-bias stress in which no Cu-ion drift occurs. It is concluded that Cu-ion drift is suppressed by a 10 nm thick CoWP barrier.

In Situ Monitoring of Silicon Surfaces During Reactive Ion Etching

Surface chemical reactions during reactive ion etching (RIE) of silicon in a CF4+O2 plasma have been investigated by employing in situ Fourier-transform infrared attenuated total reflection (FT-IR ATR) spectroscopy. It is shown that a surface reaction layer with a thickness of 2–4 nm is composed of SiFX (X=1, 2, 4 and presumably 3) and SiOY (Y< 2) bonds. The SiFX bond concentrations in the surface reaction layer are almost independent of O2 gas concentration in the plasma because they are located mainly at the subsurface layer/Si interface. The etch rate is determined by the oxidized subsurface layer thickness and fluorine radical flux penetrating into the interface region, where the etch products SiFX are formed.

Integration of Self-Assembled Porous Silica in Low-

Integration of a self-assembled porous silica film layered with a cap film was carried out for low-k/Cu damascene structures. The dielectric constant of the porous silica in the layered damascene structure was extracted, and the process-induced damage layer was characterized. Due to the integration process of low-k/Cu damascene, the hydrophobic methyl group was decomposed by plasma etching and subsequent barrier and seed sputtering as well as by Cu electroplating, resulting in the formation of hydrophilic silanol groups. The lateral dimension of the process-induced damaged layer and its effective dielectric constant were found to be 35 nm and 10, respectively.

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Hydrogenated amorphous silicon (a-Si:H) was deposited using a triode-type reactor to which an intermittent substrate bias was applied. The total bonded hydrogen content was reduced to 2.9 at.% at a substrate temperature of 200°C, and a photosensitivity of 5×106 with a dark conductivity of 7×10-11 S/cm was obtained. The defect density measured using a constant photocurrent method was as low as 8.5×1015 cm-3. It is suggested that the ion flux intermittently impinging onto the growing film surface causes ion-induced hydrogen desorption and a-Si:H network relaxation.

/Cu Damascene Interconnects

Advanced Semiconductor Research Center (ASRC), National Institute of Advanced Science and Technology (AIST), 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan; E-mail: n.hata@aist.go.jp Millennium Research for Advanced Information Technology (MIRAI)-ASRC, AIST, 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan MIRAI-Association of Super Advanced Electronics Technologies (ASET), 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan Research Center for Nanodevices and Systems, Hiroshima U., 1-4-2 Kagamiyama, Higashi-Hiroshima, Hiroshima 739-8527, Japan