Jun Kawahara

Effects of material interfaces in Cu/low-/spl kappa/ damascene interconnects on their performance and reliability

The performance and reliability of Cu/Low-/spl kappa/ damascene interconnects are investigated from the view point of the material interface structure. We are focusing especially on the heterointerfaces between the Cu and the barrier metal (BM), as well as between the hard mask (HM) and the capping barrier dielectrics (CAP) covered on the Cu interconnects. It is found that the highest via reliabilities of electromigration (EM) and thermal cycle are established by the barrier-metal-free (BMF) structure without the heterointerface between the Cu and the BM due to the strong Cu-to-Cu connection at the via bottom. The interline time-dependant dielectric breakdown lifetime is improved mostly by using a HM with the same materials as the CAP layer, referred to as an unified structure, which diminishes the heterointerface between the HM and the CAP. These ideal structures without the material heterointerfaces derive the highest reliability and performance. Structural control of the material heterointerfaces in the actual Cu/low-/spl kappa/ damascene interconnect is crucial for the high reliability and performance.

Highly thermal-stable, plasma-polymerized BCB polymer film

A new plasma-enhanced organic monomer-vapour polymerization (plasma polymerization) method has been developed. It was used to make a divinyl siloxane bis-benzocyclobutene (DVS-BCB) polymer film for Cu dual-damascene interconnects that had high thermal stability and a low dielectric constant, k = 2.6. The method consists of the vaporization of organic monomers, transportation of monomers in the gas phase, and polymerization by plasma to make the polymer film. The method eliminates polymer oxidation of DVS-BCB during the polymerization in high vacuum, which improves the films thermal stability. The thermal stability of plasma-polymerized BCB (p-BCB) exceeded 400°C because of the higher deposition temperature, and the film had a high resistance to Cu diffusion at 400°C annealing. The narrow-pitched Cu/BCB damascene lines showed a 35% reduction in line capacitance compared with Cu/SiO2 ones. The p-BCB is shown to be a strong candidate for Cu/low-k interconnects.

Barrier-metal-free (BMF), Cu dual-damascene interconnects with Cu-epi-contacts buried in anti-diffusive, low-k organic film

Barrier-metal-free (BMF) Cu dual-damascene interconnects (DDI) are fabricated in the plasma-polymerized, divinyl siloxane bis-benzocyclobutene (p-BCB: k=2.6) polymer film, which is characterised by anti-diffusive characteristics for the Cu. The BMF-structure has inter-line leakage current as low as that of a conventional barrier-inserted structure and is estimated to retain the high insulating properties for over 10 years under 1 MV/cm stress. The BMF-structure also derives Cu-epi-contacts, reducing the via-resistance to 50% of that of the conventional Cu/barrier/Cu contacts. The effective dielectric constant was k/sub eff/=3.1, including very thin SiN etch-stop-layers, accomplishing 20% faster CMOS device operation compared to that of the conventional Cu-DDI in the SiO/sub 2/ with Ta-TaN barriers. The BMF Cu-DDIs buried directly in the p-BCB film is one of the ultimate structures for high performance, 0.1 /spl mu/m-CMOS devices and beyond.

High performance Cu interconnects with low-k BCB-polymers by plasma-enhanced monomer-vapor polymerization (PE-MVP) method

A new plasma-enhanced organic monomer-vapor polymerization (PE-MVP) method is developed for deposition of divinyl siloxane bis-benzocyclobutene (DVS-BCB) polymer films with low dielectric constant, k=2.7. The PE-MVP method eliminates polymer oxidation of DVS-BCB during polymerization, improving the thermal stability. By combining the MOCVD-Cu technique with the PE-MVP, narrow-pitch Cu/BCB damascene lines reveal a 35% reduction in the line capacitance compared to Cu/SiO/sub 2/ lines, while the interline leakage current is kept as low as 5/spl times/10/sup -9/ A/cm/sup 2/.

Feasibility study of a novel molecular-pore-stacking (MPS), SiOCH film in fully-scale-down, 45nm-node Cu damascene interconnects

Molecular-pore-stacking (MPS), SiOCH films (k=2.4) are integrated in 45nm-node Cu interconnects with 140nm-pitched lines and 70nm-vias, and the feasibility is confirmed. The MPS film, which is deposited by plasma-polymerization of robust ring-type siloxane molecules, has the self-organized, porous structure with reinforcing the mechanical properties. The low permittivity is sustained in the 140nm-pitched lines by oxidation-damage-free etching, and the inter-line dielectric reliability is confirmed along with the BCB pore-seal technique, estimating 15.9% reduction in the 70nm-spaced, line capacitance refer to that of the 65nm-node SDIs. The MPS/Cu interconnect is one of the strong candidates for 45nm-node ULSI devices.

Highly thermal-stable, plasma-polymerized BCB polymer film (k=2.6) for Cu dual-damascene interconnects

Highly thermal-stable, plasma-polymerized divinyl siloxane bis-benzocyclobutene (p-BCB)-polymer film is developed for Cu dual-damascene interconnects. The thermal stability of p-BCB is improved over 400/spl deg/C by higher deposition temperature, having high resistance to Cu diffusion at 400/spl deg/C-annealing. Lowering the RF plasma-power and the deposition pressure, the p-BCB film has smaller dielectric constant than the conventional spin-coating BCB (k=2.7). The p-BCB (k=2.6)/Cu interconnects reveal 46% delay reduction of CMOS ring oscillator to the conventional SiO/sub 2//Al ones. The p-BCB is proved as a strong candidate for Cu/low-k interconnects.

A new direct low-k/Cu dual damascene (DD) contact lines for low-loss (LL) CMOS device platforms

A new direct low-k/Cu dual damascene (DD) contact line has been developed for low loss (low parasitic capacitance and low resistance) CMOS device platforms by on-current BEOL technologies. The excellent low contact resistance is realized in the low-k pre-metal-dielectrics (PMD) with a reduced aspect ratio, achieving 5.4 Omega for 75 nmphi contact which is only 1/4 relative to a conventional W-plug. The CMOS active performance was improved with no reliability degradation, featuring in cost-effective RF/ubiquitous applications.