Yoshito Sakurai

A shared buffer memory switch for an ATM exchange

The authors propose a shared buffer memory switch in which output buffer memories are shared by all the switch output ports and are alloted to one particular output port as the occasion demands. This switch architecture can further improve the hardware-utilization efficiency of the memory switch by increasing the buffer memory usage rate. A discussion on switch traffic characteristics is provided and indicates that buffer sharing reduced the required memory size to less than 0.14 of that otherwise required for adequate switch size and estimates roughly the buffer size required for the switch. The large scale integration (LSI) count, for example, is about 15 chips for the main part of a 32*32 switch (150 Mb/s for each port) which can be mounted on one printed board. The switch is partitioned into a buffer memory LSI and a control LSI to make them flexible to change in ATM switch specifications.<<ETX>>

32*32 shared buffer type ATM switch VLSIs for B-ISDNs

A set of 0.8 mu m CMOS VLSIs developed for shared buffer switches in asynchronous transfer mode (ATM) switching systems is described. A 32*32 unit switch consists of eight buffer memory VLSIs, two memory control VLSIs, and two commercially available first in first out (FIFO) memory LSIs. Using the VLSIs, the switch can be mounted on a printed board. To provide excellent traffic characteristics not only under random traffic conditions but also under burst traffic conditions, this switch has a 2-Mb shared buffer memory, the largest reported to date. which can save 4096 cells among 32 output ports. This switch has a priority control function to meet the different cell loss rate requirements and switching delay requirements of different service classes. A multicast function and a 600 Mb/s link switch architecture, which are suitable for ATM network systems connecting various media, and an expansion method using the 32*32 switching board to achieve large-scale switching systems such as 256*256 or 1024*1024 switches are discussed. >

Large-scale ATM multistage switching network with shared buffer memory switches

The configuration of an asynchronous transfer mode (ATM) switch architecture using a shared buffer memory switch (SBMS) is discussed. The scaling factors of the ATM switching network under a condition of mixed applications, including a conventional mix and telecommunication with video, are analyzed. The use of the SBMS as the unit switch for a multistage switching network is examined. A prototype system and its performance evaluation and experimental data are presented. The data indicate excellent performance under a burst cell arrival condition. The buffer size of the SBMS can be reduced in comparison with that of an individual (nonshared) buffer memory switch. A configuration for a large-scale ATM switching network with multistage switches is proposed.<<ETX>>

Large scale atm multi-stage switching network with shared buffer memory switches

This paper discusses the configuration of an ATM(Asynchronous Transfer Mode) switching network with a shared buffer memory switch (SBMS) which has the potential to provide good traffic characteristics and easy LSI implementation. The scaling factors of the ATM switching network under a condition of mixed applications are discussed first. Then the SBMS as the unit element ofthe multi-stage switching network is described, and its performance evaluation and experimental data are introduced. The data indicate excellent performance under burst cell arrival condition. Last a concept of a large scale ATM switching network configuration with multi-stage switches is proposed. The non blocking condition in ATM multi-stage switching network as an alternative resource management scheme is described.

32*32 shared buffer type ATM switch VLSIs for B-ISDN

A set of 0.8 mu m CMOS VLSIs developed for shared buffer switches in asynchronous transfer mode (ATM) switching systems is described. A unit switch, whose size is 32*32, consists of 8 buffer memory LSIs (BFM-LSIs), 2 memory control LSIs (CTRL-LSIs) and 2 commercially available first in, first out (FIFO) memory LSIs. Using these VLSIs, the 32*32 switch can be mounted on a printed board. This switch is a shared buffer switch. It achieves buffer memory utilization improvement through the use of buffer sharing among all output ports of the switch and has a large 2-Mbit shared buffer which can save 4096 cells. As a result, this switch can satisfy the cell loss rate requirements, not only under random traffic conditions but also under burst traffic conditions. The switch has a priority control function to meet the requirements for various media. It is useful for multimedia ATM networks.<<ETX>>

A large scale ATM switching system architecture for multimedia communications

1 . Introduction Multimedia communications are having a great impact on switching system architecture . The Asynchronous Transfer Mode (ATM) is the predominant technique used to obtain a B-ISDN with a universal interface . Next-generation switching using this technique must have a flexible architecture to handl e the heterogeneous traffic and sophisticated services multimedia communications will provide . To adapt to the increase of B-ISDN subscribers, we propose a hyper-distributed switching system architecture composed of a non-intelligent module and independent modules with call processing functions . To multiplex burst traffic , ATM shared buffer memory switches are used as the unit switches in both modules .