Shinobu Gohara

Shared buffer memory switch for an ATM exchange

An asynchronous transfer mode (ATM) switch architecture called a shared buffer memory switch whose output cell buffers are shared among all the output ports of the switch is proposed. Experimental measurements and a discussion about the traffic characteristics of the switch architecture are carried out to determine how much buffer memory will be reduced through buffer sharing under various traffic conditions and to roughly estimate how many buffers are needed for the switch to meet certain requirements. The resultant estimate shows that buffer sharing reduces the necessary buffer memory to less than 1/5 of what would otherwise be required, and the required buffer size is about 128 cells/output for a 32*32 switch when considering bursty traffic conditions. LSI implementation is also discussed to show that a 32*32 switch can be composed of about 12 chips mounted on one printed board. >

A shared buffer memory switch for an ATM exchange

The authors propose a shared buffer memory switch in which output buffer memories are shared by all the switch output ports and are alloted to one particular output port as the occasion demands. This switch architecture can further improve the hardware-utilization efficiency of the memory switch by increasing the buffer memory usage rate. A discussion on switch traffic characteristics is provided and indicates that buffer sharing reduced the required memory size to less than 0.14 of that otherwise required for adequate switch size and estimates roughly the buffer size required for the switch. The large scale integration (LSI) count, for example, is about 15 chips for the main part of a 32*32 switch (150 Mb/s for each port) which can be mounted on one printed board. The switch is partitioned into a buffer memory LSI and a control LSI to make them flexible to change in ATM switch specifications.<<ETX>>

Large-scale ATM multistage switching network with shared buffer memory switches

The configuration of an asynchronous transfer mode (ATM) switch architecture using a shared buffer memory switch (SBMS) is discussed. The scaling factors of the ATM switching network under a condition of mixed applications, including a conventional mix and telecommunication with video, are analyzed. The use of the SBMS as the unit switch for a multistage switching network is examined. A prototype system and its performance evaluation and experimental data are presented. The data indicate excellent performance under a burst cell arrival condition. The buffer size of the SBMS can be reduced in comparison with that of an individual (nonshared) buffer memory switch. A configuration for a large-scale ATM switching network with multistage switches is proposed.<<ETX>>

Large scale atm multi-stage switching network with shared buffer memory switches

This paper discusses the configuration of an ATM(Asynchronous Transfer Mode) switching network with a shared buffer memory switch (SBMS) which has the potential to provide good traffic characteristics and easy LSI implementation. The scaling factors of the ATM switching network under a condition of mixed applications are discussed first. Then the SBMS as the unit element ofthe multi-stage switching network is described, and its performance evaluation and experimental data are introduced. The data indicate excellent performance under burst cell arrival condition. Last a concept of a large scale ATM switching network configuration with multi-stage switches is proposed. The non blocking condition in ATM multi-stage switching network as an alternative resource management scheme is described.