You-Keun Han

Implementation of power transmission lines to field programmable gate array ICs for managing signal and power integrity

As the operating frequencies of electronic devices increase, power and signal integrity have become a major issue. Simultaneous switching noise (SSN) is a major problem that restricts the performance of high speed digital systems. SSN leads to voltage fluctuations during data transitions which can induce excessive noise. SSN is caused by parasitic inductance components in the power delivery network (PDN) that manifest themselves through via transitions, apertures on reference plane, split planes and even solid planes. A new method has been proposed to address this problem, which employs power transmission lines (PTL) that supply power to integrated circuits instead of using the conventional power/ground plane pairs. This along with current balancing can be used to manage return path discontinuities and power supply noise. Many of the published work in this area have proved that the PTL concept is able to reduce SSN and enhance power and signal integrity. Pseudo-balanced power transmission line (PB-PTL) concept has been shown to improve performance and reduce power consumption. However, this has only been applied to relatively simple test vehicles. In this paper, the PB-PTL scheme has been extended for driving multiple I/O drivers in field programmable gate array (FPGA) ICs. This paper discusses the theory, simulation and measurement results for this implementation.

Managing signal and power integrity using power transmission lines and alternative signaling schemes

Signal and power integrity are crucial for ensuring good performance in high speed digital systems. As the operating frequency of digital systems increases, the power and ground bounce created by simultaneous switching noise (SSN) becomes a limiting factor for the performance of these devices. SSN is caused by parasitic inductance that exists in the power delivery network (PDN), and voltage fluctuations on the power and ground rails can lead to reduced noise margins and can limit the maximum frequency of a digital device. A new PDN design has been suggested that achieves significantly reduced SSN [1] by replacing the power plane structure with a power transmission line (PTL). Previous works have demonstrated the validity of the Power Transmission Line concept in terms of SSN reduction and power consumption reduction [1-4]. However, these works focused on small systems with just a few bits. This paper shows the effectiveness of the PTL concept on a large scale system with a large number of I/O pins through an FPGA implementation to simulate the memory interface such as DDR3.