Byung-se So

Electrical Extractions of One Dimensional Doping Profile and Effective Mobility for Metal--Oxide--Semiconductor Field-Effect Transistors

In this study, an attempt is made to provide a framework to assess and improve metal–oxide–semiconductor field-effect transistor (MOSFET) reliability from the early stage of the design to the completion of the product. A small gate area has very small capacitances that are difficult to measure, making capacitance–voltage (C–V) based techniques difficult or impossible. In view of these experimental difficulties, we tried electrical doping profiling measurement for MOSFET with short gate length, ultra thin oxide thickness and asymmetric source/drain structure and checked the agreement with simulation result. We could get the effective mobility by simple drain current versus drain bias voltage measurement. The calculated effective mobility was smaller than expected value and we explained some reasons. An accurate effective mobility for asymmetric source–drain junction transistor was successfully extracted by using the split C–V technique, with the capacitance measured between the gate and source–drain and between the gate and the substrate.

The effect of Cu contamination on device reliability in DRAM

Effects of copper (Cu) contamination on device reliability in DRAM have been investigated. With device size scaling, copper-related dielectric degradation becomes one of the most important concerns due to the scaled dielectric thicknesses. The Cu out-diffusion from the direct contact (DC) bottom to the adjacent gate was observed for the failed samples with high temperature storage (HTS) stressing. HTS tests were performed at various temperatures to extract the activation energy for HTS failure. The predicted lifetime for the samples with Cu contamination was found to be 12 years at normal operating condition without stressing bias. Even though the root cause of the Cu contamination was not clearly revealed, based on the diffusion distance of Cu in silicon (Si), we speculated that the Cu contamination can be caused by the Cu migration into Si from the backside of wafer when the contamination was involved with one of packaging processes.

Thermal characterization of high speed DDR devices in system environments [DRAM modules]

This paper studies the thermal characteristics of various memory modules for desktop and server systems. Using a CFD (computational fluid dynamics) simulator, we simulated these modules to predict their junction temperature. A detailed simulation model and power calculation procedures are described. Simulation results are provided for different conditions and parameter variations. Also, thermal measurements of these modules were carried out in real systems. The simulation and measured data were compared, and the results proved that the simulation model was sufficiently accurate for use in memory subsystem thermal design. Using the proposed simulation model of these modules and analysis results, the minimum requirements were defined for avoiding thermal problems in newly designed memory modules.

Gate oxide integrity by initial gate current

A new and accurate approach to gate oxide reliability measurements for the determination of the gate oxide quality and lifetime estimation on MOSFET is presented. An accurate gate oxide thickness calculation by gate current provides oxide thickness variations better than conventional CV measurement. A gate oxide quality by gate current analysis is well correlated to the time dependent dielectric breakdown (TDDB) method. The results present that oxide lifetime is better at lower gate current in same oxide thickness where device process is same but different fabrication facilities (FAB).